ISL26132_14 Datasheet, PDF (20/23 Pages) Intersil Corporation – Low-Noise 24-bit Delta Sigma ADC

+5V
5M
TYPE K
5M
ISL26132, ISL26134
ISL21009
4.096V
10nF
10k
10k
1µF
0.1µF
18
AVDD
16 _VREF+
11 AIN+1
1
DVDD
GAIN1 ²⁰
GAIN0 ¹⁹
SDO/RDY ²⁴
SCLK ²³
PDWN ²²
XTALOUT ⁴
12
14
13
AIN-1
AIN+2
AIN-2
XTALIN/CLOCK
SPEED
A0
3
21
8
15 _VREF-
TEMP ⁷
AGND
DGND
17
2, 5, 6
+3V
0.1µF
MICRO
CONTROLLER
4.9152
MHz
FIGURE 39. THERMOCOUPLE MEASUREMENT APPLICATION
THERMOCOUPLE MEASUREMENT
Figure 39 illustrates the ISL26132 in a thermocouple
application. The 4.096V reference combined with the PGA gain
set to 128x sets the input span of the converter to ±16mV. This
supports the K type thermocouple measurement for
temperatures from -270°C at -6.485mV to +380°C at about
16mV.
If a higher temperature is preferred, the PGA can be set to 64x to
provide a converter span of ±32mV. This will allow the converter
to support temperature measurement with the K type
thermocouple up to about +765°C.
Figure 39 shows that the thermocouple is referenced to a voltage
dictated by the resistor divider from the +5V supply to ground.
These set the common mode voltage at about 2.5V. The 5M
resistors provide a means for detection of an open thermocouple.
If the thermocouple fails to open or is not connected, the bias
through the 5M resistors will cause the input to the PGA to go to
full scale.
PCB Board Layout and System
Configuration
The ISL26132, ISL26134 ADC is a very low noise converter. To
achieve the full performance available from the device will
require attention to the printed circuit layout of the circuit board.
Care should be taken to have a full ground plane without
impairments (traces running through it) directly under the chip
on the back side of the circuit board. The analog input signals
should be laid down adjacent (AIN+ and AIN- for each channel) to
achieve good differential signal practice and routed away from
any traces carrying active digital signals. The connections from
the CAP pins to the off-chip filter capacitor should be short, and
without any digital signals nearby. The crystal, if used, should be
connected with relatively short leads. No active digital signals
should be routed near or under the crystal case or near the
traces, which connect it to the ADC. The AGND and DGND pins of
the ADC should be connected to a common solid ground plane.
All digital signals to the chip should be powered from the same
supply, as that used for DVDD (do not allow digital signals to be
active high unless the DVDD supply to the chip is alive). Route all
active digital signals in a way to keep distance from any analog
pin on the device (AIN, VREF, CAP, AVDD). Power on the AVDD
supply should be active before the VREF voltage is present.
PCB layout patterns for the chips (ISL26132 and ISL26134) are
found on the respective package outline drawings on pages 22
and 23.
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FN6954.3
November 20, 2014