ISL26132_14 Datasheet, PDF (18/23 Pages) Intersil Corporation – Low-Noise 24-bit Delta Sigma ADC

ISL26132, ISL26134
Operation of PDWN
PDWN must transition from low to high after both power supplies
have settled to specified levels in order to initiate a correct
power-up reset (Figure 35). This can be implemented by an
external controller or a simple RC delay circuit, as shown in
Figure 36.
In order to reduce power consumption, the user can assert the
Power-down mode by bringing PDWN Low as shown in Figure 37.
All circuitry is shut down in this mode, including the Crystal
Oscillator. After PDWN is brought High to resume operation, the
reset delay varies depending on the clock source used. While an
external clock source will resume operation immediately, a
circuit utilizing a crystal will incur about a 20ms delay due to the
inherent start-up time of this type of oscillator.
AVDD
DVDD
PDWN
10µs
FIGURE 35. POWER-DOWN TIMING RELATIVE TO SUPPLIES
D_VDD
1k
2.2nF
CONNECT TO
PDWN PIN
FIGURE 36. PDWNDELAY CIRCUIT
PDWN
SDO/RDY
SCLK
POWER-DOWN
MODE
tt1₁4₄
CLK
SOURCE
WAKEUP
START
DATA
CONVERSION READY
t₁₃
t₁₁
FIGURE 37. POWER-DOWN MODE WAVEFORMS
PARAMETER
t₁₃
t₁₄
TABLE 14. POWER-DOWN RECOVERY TIMING
DESCRIPTION
Clock Recovery after PDWN Internal Oscillator
High
External Clock Source
4.9152MHz Crystal
Oscillator
PDWN Pulse Duration
TYP
7.95
0.16
5.6
26
UNITS
µs
µs
ms
µs (min)
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FN6954.3
November 20, 2014