ISL26132_14 Datasheet, PDF (15/23 Pages) Intersil Corporation – Low-Noise 24-bit Delta Sigma ADC

ISL26132, ISL26134
V_IN
SDO/RDY
Start of
conversion
Abrupt Change in External V_IN
1st conversion;
includes
unsettled V_IN
2nd conversion;
V_IN settled,
Digital filter
unsettled
3rd conversion;
V_IN settled,
Digital filter
unsettled
4th conversion;
V_IN settled,
Digital filter
unsettled
5th conversion;
V_IN and Digital,
filter settled
Conversion
time
FIGURE 29. SDO/RDY DELAY AFTER MULTIPLEXER CHANGE
Conversion Data Rate
The SPEED pin is used to select between the 10Sps and 80Sps
conversion rates. The 10Sps rate (SPEED = Low) is preferred in
applications requiring 50/60Hz noise rejection. Note that the
sample rate is directly related to the oscillator frequency, as
491,520 clocks are required to perform a conversion at the
10Sps rate, and 61,440 clocks at the 80Sps rate.
Output Data Format
The 24-bit converter output word is delivered in two’s
complement format. Input exceeding full scale results in a
clipped output which will not return to in-range values until after
the input signal has returned to the specified allowable voltage
range and the digital filter has settled as discussed previously.
TABLE 9. OUTPUT CODES CORRESPONDING TO INPUT
INPUT SIGNAL
OUTPUT CODE (HEX)
+0.5V_REF/GAIN
(+0.5V_REF/GAIN)/(2²³ - 1)
0
(-0.5V_REF/GAIN)/(2²³ - 1)
-0.5V_REF/GAIN
7FFFFF
000001
000000
FFFFFF
800000
Reading Conversion Data from the Serial
Data Output/Ready SDO/RDY Pin
When the ADC is powered, it will automatically begin doing
conversions. The SDO/RDY signal will go low to indicate the
completion of a conversion. After the SDO/RDY signal goes low,
the MSB data bit of the conversion word will be output from the
SDO/RDY pin after SCLK is transitioned from a low to a high.
Each subsequent new data bit is also output on the rising edge of
SCLK (see Figure 30). The receiving device should use the falling
edge of SCLK to latch the data bits. After the 24th SCLK, the
SDO/RDY output will remain in the state of the LSB data bit until
a new conversion is completed. At this time, the SDO/RDY will go
high if low and then go low to indicate that a new conversion
word is available. If not all data bits are read from the SDO/RDY
pin prior to the completion of a new conversion, they will be
overwritten. SCLK should be low during time t₆, as shown in
Figure 30, when SDO/RDY is high.
If the user wants the SDO/RDY signal to go high after reading the
24 bits of the conversion data word, a 25th SCLK can be issued.
The 25th SCLK will force the SDO/RDY signal to go high and
remain high until it falls to signal that a new conversion word is
available. Figure 31 illustrates the behavior of the SDO/RDY
signal when a 25th SCLK is used.
DATA READY
SDO/RDY
DATA
MSB
23 22 21
LSB
0
NEW DATA READY
t₄
t5
t₂
t₃
t₆
SCLK
1
24
t₃
t₇
FIGURE 30. OUTPUT DATA WAVEFORMS USING 24 SCLKS TO READ CONVERSION DATA
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FN6954.3
November 20, 2014