ISL6617_14 Datasheet, PDF (2/15 Pages) Intersil Corporation – PWM Doubler with Phase Shedding Function and Output Monitoring Feature

ISL6617
Functional Pin Descriptions
PIN # PIN SYMBOL
FUNCTION
1
ISENA+ Output of the differential amplifier for Channel A. Connect a resistor on this pin to the negative rail of
the sensed voltage to set the current gain.
2
ISENA- Input of the differential amplifier for Channel A. Typically, the positive rail of sensed voltage via DCR
sensing network connects to this node.
3
PWMIN The PWM input signal triggers the J-K flip flop and alternates its input to channel A and B. Both channels
are effectively modulated. The PWM signal can enter three distinct states during operation, see
Operation section for further details. Connect this pin to the PWM output of the controller. The pin is
pulled to VCC when EN_PH_SYNC is low.
4
ISENB+ Output of the differential amplifier for Channel B. Connect a resistor on this pin to the negative rail of
the sensed voltage to set the current gain.
5
ISENB- Input of the differential amplifier for Channel B. Typically, the positive rail of sensed voltage via DCR
sensing network connects to this node.
6
PWMB
PWM output of Channel B with Tri-state feature.
7 EN_PH_SYNC Driver Enable and Mode Selection Input. See Enable and Mode Operation for more details.
8
IOUT
Current monitoring Output. It sources out the average current of both Channel A and B.
9
VCC
Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality
low ESR ceramic capacitor from this pin to GND.
10
PWMA
PWM output of Channel A with Tri-state feature.
11
GND
Bias and reference ground. All signals are referenced to this node. Place a high quality low ESR ceramic
capacitor from this pin to VCC. Connect this pad to the power ground plane (GND) via thermally
enhanced connection.
Block Diagram
VCC
PWMIN
EN_PH_SYNC
GND
IOUT
55k
48k
CONTROL
LOGIC
CURRENT
BALANCE BLOCK
ISENA-
ISENA+
PWMA
CHANNEL A
PWMB
ISENB-
ISENB+
CHANNEL B
2
FN7564.0
February 4, 2010