ISL6617_14 Datasheet, PDF (11/15 Pages) Intersil Corporation – PWM Doubler with Phase Shedding Function and Output Monitoring Feature

ISL6617
When the doubler operates in interleaving mode, the
PWM controller frequency should be set at two times the
desired phase frequency (F_SW). Since the input PWM
pulse is divided into half to feed into each phase of the
doubler, the operational duty cycle of each phase should
be less than 50%. In synchronous mode, the PWM
controller should be operated at the same frequency as
the desired phase frequency. In this mode, the allowable
duty cycle is up to 100%. For cascaded interleaving, the
controller switching frequency needs to be set at four
times the phase frequency. During cascaded operation,
the maximum allowable duty cycle will be less than 25%.
All of the maximum allowable duty cycle numbers
referenced assume that the PWM controller can send out
a 100% duty cycle pulse. In many cases, this is not
achievable because the controller needs time to reset it's
internal sawtooth ramp or internal max duty limit.
However, the fixed 120ns extension of interleaving mode
2 helps recover the typical 1% duty cycle loss associated
with the ramp reset time. In addition, Intersil has
developed a dedicated controller, the ISL6336G with
90% duty cycle, to work with the ISL6617 for high-phase
count and overclocking applications.
PWM1
PWMA
PWM1A
PWM1B
PWMB
PWM1C
PWM1D
FIGURE 9. CASCADED DOUBLER OPERATIONAL
WAVEFORMS
To properly compensate the system that uses phase
doublers, the effective system sawtooth to calculate the
modulator gain should factor in the duty cycle limitation
(D_MAX) as Equation 1. For instance, when using
ISL6336G and ISL6617s in cascaded interleaving mode,
the effective sawtooth amplitude should be scaled as
3V/22.5% = 13.33V.
V _{R A M P _EFFECTIVE}
=
V_{-----R----A----M-----P--}
D_MAX
(EQ. 1)
Current Sensing
The ISL6617 senses current continuously for fast
response. The ISL6617 supports inductor DCR sensing,
or resistive sensing techniques. The associated channel
current sense amplifier uses the ISEN inputs to
reproduce a signal proportional to the inductor current,
I_L. The sensed current, I_SEN, is proportional to the
inductor current. The sensed current is used for current
balance and load-line regulation.
The internal circuitry, shown in Figures 10 and 11,
represents one channel. This circuitry is repeated for
each channel in the doubler. The input bias current of the
current sensing amplifier is typically 60nA; less than 5kΩ
input impedance is preferred to minimize the offset error.
In addition, the common mode input voltage to the
amplifier should be less than VCC-3V.
A. INDUCTOR DCR SENSING
An inductor’s winding is characteristic of a distributed
resistance, as measured by the DCR (Direct Current
Resistance) parameter. Consider the inductor DCR as a
separate lumped quantity, as shown in Figure 10.
V_IN
IL(s)
POWER
STAGE
L
DCR
INDUCTOR
V_L
V_OUT
C_OUT
V_C(s)
PWMA/B
R
C
ISL6617
I_A/B
R_ISEN(A/B)
CURRENT
SENSE
+
ISEN-(A/B)
-
ISEN+(A/B)
C_T
I_SEN
=
I_L
---^D----^C-----^R-----
R_ISEN
FIGURE 10. DCR SENSING CONFIGURATION
The channel current I_L, flowing through the inductor, will
also pass through the DCR. Equation 2 shows the s-
domain equivalent voltage across the inductor V_L.
V_L(s) = I_L ⋅ (s ⋅ L + DCR)
(EQ. 2)
A simple R-C network across the inductor extracts the
DCR voltage, as shown in Figure 10.
The voltage on the capacitor V_C, can be shown to be
proportional to the channel current I_L. See Equation 3.
V_C(s)
=
⎝⎛^s
⋅
------^L-------
DCR
+
1_⎠⎞
⋅
(DCR
⋅
I_L)
--------------------------------------------------------------------
(s ⋅ RC + 1)
(EQ. 3)
If the R-C network components are selected such that
the RC time constant matches the inductor time constant
(RC = L/DCR), the voltage across the capacitor V_C is
equal to the voltage drop across the DCR, i.e.,
proportional to the channel current.
With the internal low-offset current amplifier, the
capacitor voltage V_C is replicated across the sense
11
FN7564.0
February 4, 2010