ISL6617_14 Datasheet, PDF (1/15 Pages) Intersil Corporation – PWM Doubler with Phase Shedding Function and Output Monitoring Feature

PWM Doubler with Phase Shedding Function and
Output Monitoring Feature
ISL6617
The ISL6617 utilizes Intersil’s proprietary Phase Doubler
scheme to modulate two-phase power trains with single
PWM input. It doubles the number of phases that
Intersil’s multi-phase controllers ISL63xx can support.
When the enable pin (EN_PH_SYNC) is pulled low, the
PWM input is pulled high. This simplifies the phase
shedding implementation for some Intersil controllers
(VR10, VR11, VR11.1, and VR12 family) that can disable
the respective and higher phase(s) by pulling the
respective PWM line high.
The ISL6617 is designed to minimize the number of
analog signals that interface between the controller and
drivers in high phase count scalable applications. The
common COMP signal, which is usually seen in
conventional cascaded configuration, is not required; this
improves noise immunity and simplifies the layout.
Furthermore, the ISL6617 provides low part count and
low cost advantage over the conventional cascaded
technique.
By cascading the ISL6617 with another ISL6617 or
ISL6611A, it can quadruple the number of phases that
Intersil’s multi-phase controllers ISL63xx can support.
The ISL6617 also features Tri-State input and outputs
that recognize a high-impedance state, working together
with Intersil multiphase PWM controllers and driver
stages to prevent negative transients on the controlled
output voltage when operation is suspended. This feature
eliminates the need for the schottky diode that may be
utilized in a power system to protect the load from
excessive negative output voltage damage.
Features
• Proprietary Phase Doubler scheme with Phase
Shedding Function (Patent Pending)
• Enhanced Light to Full Load Efficiency
• Double or Quadruple Phase Count
• Patented Current Balancing with DCR Current
Sensing and Adjustable Gain
• Current Monitoring Output (IOUT) to Simplify
System Interface and Layout
• Triple-Level Enable Input for Mode Selection
• Dual PWM Output Drives for Two Synchronous
Rectified Bridges with Single PWM Input
• Channel Synchronization and Two Interleaving Options
• Tri-State PWM Input and Outputs for Output Stage
Shutdown
• Phase Enable Input and PWM Forced High Output to
Interface with Intersil’s Controller for Phase Shedding
• Overvoltage Protection
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Utilization, Thinner Profile
- Pb-Free (RoHS Compliant)
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Applications
• High Current Low Voltage DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
• High Phase Count and Phase Shedding Applications
• 5V PWM Input Integrated Power Stage or DrMOS
Pin Configuration
February 4, 2010
1
FN7564.0
ISL6617
(10 LD DFN)
TOP VIEW
ISENA+ 1
ISENA- 2
PWMIN 3
ISENB+ 4
ISENB- 5
11
GND
10 PWMA
9 VCC
8 IOUT
7 EN_PH_SYNC
6 PWMB
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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