ISL6617_14 Datasheet, PDF (13/15 Pages) Intersil Corporation – PWM Doubler with Phase Shedding Function and Output Monitoring Feature

ISL6617
Figure 14 shows the efficiency of a 12-phase VR design,
which runs the doubler in interleaving and synchronous
modes. For comparison, a 6-phase VR with the same
number of MOSFETs and inductors is also plotted, clearly
demonstrating the efficiency improvement of a high-phase
count system and interleaving mode over synchronous
mode resulting from the better ripple cancellation.
20 ₂₀
15 15
10 10
55
24 CHANNELS, 6 INTERLEAVING
24 CHANNELS, 8 INTERLEAVING
24 CHANNELS, 12 INTERLEAVING
24 INTERLEAVING PHASES
80
24 CHANNELS, 6 INTERLEAVING
60
24 CHANNELS, 8 INTERLEAVING
40
24 CHANNELS, 12 INTERLEAVING
24 INTERLEAVING PHASES
20
00 ₀
10
20
30
40
50
DUTY CYCLE (%)
FIGURE 12. INPUT CURRENT RIPPLE VS DUTY CYCLE,
PHASE COUNT
0
0
10
20
30
40
50
DUTY CYCLE (%)
FIGURE 13. OUTPUT CURRENT RIPPLE VS DUTY CYCLE,
PHASE COUNT
93
92
91
90
PHASE DOUBLER IN
INTERLEAVING MODE
89
PHASE DOUBLER IN
SYNCHRONOUS MODE
88
6-PHASE, SAME AMOUNT
OF MOSFETS AND INDUCTORS
87
86
85
0
20 40 60 80 100 120 140 160 180
LOAD (A)
FIGURE 14. EFFICIENCY COMPARISON IN 12-PHASE DESIGN
13
FN7564.0
February 4, 2010