ISL6617_14 Datasheet, PDF (10/15 Pages) Intersil Corporation – PWM Doubler with Phase Shedding Function and Output Monitoring Feature

ISL6617
19%*R
SYNC
28.5%*R
52.5%*R
VCC
EN_PH_ SYNC
ISL6617
+
-
+
-
-
+
INTERLEAVING
0ns TO 70ns
4 CYCLES
BLANKING
INTERLEAVING
+120+(0ns TO 70ns)
SYNC
0ns TO 70ns
+
TTL
-
EN_PH
FIGURE 7. CONFIGURATION FOR TRANSITION BETWEEN SYNCHRONOUS AND INTERLEAVING #2 MODES
ISL6617/ISL6611A
PWMA ^PWM1A
VCC
EN_X
ISL6617
PWMA
ISENA
PWMA
PWMIN
PWM1B
IOUT PWMB
PHASE1A
PHASE1B
PWM1
ISENA
PWMIN
PWMB
IOUT PWMB
ISENB
PWMA ^PWM1C
PHASE1C
VOUT
ISENB
ISENA
PWMIN
PWMB ^PWM1D
IOUT
PHASE1D
VCC
EN_X _ISENB
ISL6617/ISL6611A
FIGURE 8. CASCADED PHASE DOUBLER SIMPLIFIED DIAGRAM
The ISL6617 can further be cascaded with itself or
ISL6611A (phase doubler with integrated 5V drivers), as
shown in Figure 8. This can quadruple the number of
phase each PWM line can support. Figure 9 shows the
operational waveforms of the cascaded doublers. The
PWMIN pin will be pulled to VCC when the doubler is
disabled (EN_x = Low). To avoid driving the PWM outputs
of the 1st stage ISL6617 by the 2nd stage’s PWMIN, the
2nd stage doubler’s enable input should remain high, i.e,
tied to VCC, as shown in Figure 8.
TABLE 2. CONTROLLER FREQUENCY AND MAXIMUM
DUTY CYCLE
OPERATIONAL
MODES
F_CONTROLLER
ISL6617
MAXIMUM
DUTY CYCLE
PER PHASE
D_MAX
WITH
ISL6336G
Interleaving
2 x F_SW
50%
45%
Synchronous
F_SW
100%
90%
To operate each phase at the switching frequency of F_SW,
the operational frequency of the controller needs to be
scaled accordingly for different modes, as shown in
Table 2.
Cascaded
Interleaving
4 x Fsw
25%
22.5%
10
FN7564.0
February 4, 2010