ISL70517SEH Datasheet, PDF (17/27 Pages) Intersil Corporation – Precision test and measurement

ISL70517SEH
Applications Information
“General Description” contains the ISL70517SEH functional and
performance objectives and description of operation.
“Designing with the ISL70517SEH” on page 18 contains the
application circuit design equations and guidelines for achieving
the desired DC and AC performance levels.
“Estimating Amplifier DC and Noise Performance” on page 22
provides equations for predicting DC offset voltage and noise of
the finished design.
General Description
The ISL70517SEH is an elaboration of the simpler current
feedback approach. The G_Ms are implemented with two external
resistors and very high-gain amplifiers that impose input and
feedback voltages upon them. The amplifiers have gains around
ten million and linearize the transistor’s errors well below the
10ppm level. The overall gain is (R_FB/R_IN). With very high gain in
the pseudo-G_Ms, the circuit adds little gain error and only R_FB and
R_IN set gain to the 10ppm level. Thus, only the matching of the
external resistors sets gain error and the cost of the resistors can
be tailored to the accuracy needed. Note that the input stage is
completely unaffected by output biasing, the right thing for an
instrumentation amplifier.
The ISL70517SEH instrumentation amplifier was developed to
accomplish the following:
• Provide rail-to-rail output for optimally driving ADCs. Maximum
output voltage set by R_FB (Equation 8 on page 18).
• Limit the output swing to prevent output overdrive.
• Allow any gain, including attenuation.
• Maximize gain accuracy by removing on-chip component
tolerances and external PC board parasitic resistance.
• Enable user control of amplifier precision level with choice of
external resistor tolerance.
• Maintain CMRR >100dB and remove CMRR sensitivity to gain
resistor tolerance.
• Provide a level-shift interface from bipolar analog input signal
sources to unipolar and bipolar ADC output terminations.
I1
I2
VCC
I3
I4
VCO
-
VOUT
+
VEO
IN+
+
500Ω _-
+R_IN
Q1
Q2
R_IN
IN-
+
- ^500Ω
-R_IN
+R_INSENSE
100µA
-R_INSENSE
100µA
V_REF
+
-
Q3
Q4
RFB
+ ^+VFB
-
-R_FB
+R_FB
-R_FBSENSE
100µA
100µA
+R_FBSENSE
VEE
FIGURE 48. ISL70517SEH FUNCTIONAL BLOCK DIAGRAM
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FN8699.4
December 15, 2016