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| X5323 Datasheet, PDF (16/21 Pages) Intersil Corporation – CPU Supervisor with 32Kb SPI EEPROM | |||
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X5323, X5325
RESET/RESET Output Timing
Symbol
Parameter
tWDO
tCST
tRST
Watchdog time out period,
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
CS pulse width to reset the watchdog
Reset time out
VTRIP Set Conditions
VCC
VTRIP
tTSU
tVPS
Min.
100
450
1
400
100
tTHD
tRP
tP
tVPH
CS
tVPS
tVPH
tVPO
VP
SCK
VP
SI
tVPO
Typ.
200
600
1.4
200
VTRIP Reset Conditions
VCC*
CS
SCK
SI
VCC
VP
*VCC > Programmed VTRIP
tVPS
tP
tVP1
tVPS
tVPH
tRP
tVPO
tVPO
Max.
300
800
2
300
Unit
ms
ms
sec
ns
ms
16
FN8131.1
October 27, 2005
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