X5323 Datasheet, PDF (14/21 Pages) Intersil Corporation – CPU Supervisor with 32Kb SPI EEPROM

Serial Input Timing
CS
SCK
SI
t_LEAD
t_SU
t_H
MSB IN
X5323, X5325
t_RI
t_CS
t_LAG
t_FI
LSB IN
SO
High Impedance
Serial Output Timing
Symbol
f_SCK
t_DIS
t_V
t_HO
t_RO(3)
t_FO(3)
Parameter
Clock frequency
Output disable time
Output valid from clock low
Output hold time
Output rise time
Output fall time
2.7-5.5V
Min.
Max.
0
2
250
250
0
100
100
Unit
MHz
ns
ns
ns
ns
ns
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) t_WC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Serial Output Timing
CS
SCK
t_CYC
t_WH
t_LAG
t_V
t_HO
t_WL
t_DIS
SO
MSB Out
MSB–1 Out
LSB Out
SI
ADDR
LSB IN
14
FN8131.1
October 27, 2005