X5323 Datasheet, PDF (10/21 Pages) Intersil Corporation – CPU Supervisor with 32Kb SPI EEPROM

Figure 6. Read Status Register Sequence
CS
X5323, X5325
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Instruction
SI
High Impedance
SO
Data Out
76543210
MSB
Figure 7. Write Enable Latch Sequence
CS
SCK
01234567
SI
High Impedance
SO
Figure 8. Write Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30 31
Instruction
SI
16 Bit Address
Data Byte 1
15 14 13
3 2 107 65 43 2 10
CS
SCK
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Data Byte 2
Data Byte 3
SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Data Byte N
654 321 0
10
FN8131.1
October 27, 2005