X5323 Datasheet, PDF (1/21 Pages) Intersil Corporation – CPU Supervisor with 32Kb SPI EEPROM

®
Data Sheet
X5323, X5325
(Replaces X25323, X25325)
October 27, 2005
FN8131.1
CPU Supervisor with 32Kb SPI EEPROM
FEATURES
• Selectable watchdog timer
• Low V_CC detection and reset assertion
—Five standard reset threshold voltages
—Re-program low V_CC reset threshold voltage
using special programming sequence
—Reset signal valid to V_CC = 1V
• Determine watchdog or low voltage reset with a
volatile flag bit
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
—<400µA max active current during read
• 32Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
Block Lock^™ protection
—In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—32-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
—14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
DESCRIPTION
These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Block Lock Protect Serial EEPROM
Memory in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low V_CC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when V_CC falls below the minimum V_CC trip
point. RESET/RESET is asserted until V_CC returns to
proper operating level and stabilizes. Five industry stan-
dard V_TRIP thresholds are available, however, Intersil’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
WP
SI
SO
SCK
CS/WDI
V_CC
Data
Register
Command
Decode &
Control
Logic
V_CC Threshold
Reset Logic
Watchdog Transition
Detector
Protect Logic
Status
Register
8Kbits
8Kbits
16Kbits
+
V_TRIP
-
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power-on and
Low Voltage
Reset
Generation
RESET/RESET
X5323 = RESET
X5325 = RESET
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright Intersil Americas Inc. 2005. All Rights Reserved
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