ISL6263D Datasheet, PDF (16/17 Pages) Intersil Corporation – Pre-biased Output Start-Up Capability

ISL6263D
traces and components. The paddle on the bottom of the
ISL6263D QFN package is not electrically connected to the
IC, however, it is recommended to make a good thermal
connection to the VSS island using several vias. Connect the
input capacitors, the output capacitors and the source of the
lower MOSFETs to the power ground plane.
LGATE, PVCC, and PGND
PGND is the return path for the pull-down of the LGATE
low-side MOSFET gate driver. Ideally, PGND should be
connected to the source of the low-side MOSFET with a
low-resistance, low-inductance path. The LGATE trace should
be routed in parallel with the trace from the PGND pin. These
two traces should be short, wide and away from other traces
because of the high peak current and extremely fast dv/dt.
PVCC should be decoupled to PGND with a ceramic capacitor
physically located as close as practical to the IC pins.
VIAS TO
GROUND
PLANE
GND
INDUCTOR
HIGH-SIDE
MOSFETS
VOUT
PHASE
NODE
VIN
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
FIGURE 10. TYPICAL POWER COMPONENT PLACEMENT
UGATE, BOOT, and PHASE
PHASE is the return path for the entire UGATE high-side
MOSFET gate driver. The layout for these signals require
similar treatment, but to a greater extent, than those for
LGATE, PVCC, and PGND. These signals swing from
approximately VIN to VSS and are more likely to couple into
other signals.
RBIAS
The resistor R_RBIAS should be placed in close proximity to
the ISL6263D using a noise-free current return path to the
VSS pin.
VIN
The VIN signal should be connected near the drain of the
high-side MOSFET.
IMON, SOFT, OCSET, VW, COMP, FB, VDIFF,
ICOMP, ISP, ISN and VO
The traces and components associated with these pins
require close proximity to the IC as well as close proximity to
each other. This section of the converter circuit needs to be
located above the island of analog ground with the
single-point connection to the VSS pin.
Resistor R_S
Resistor R_S is preferably located near the boundary
between the power ground and the island of analog ground
connected to the VSS pin.
VSEN and RTN
These traces should be laid out as noise sensitive. For
optimum load line regulation performance, the traces
connecting these two pins to the Kelvin sense leads of the
processor should be laid out away from rapidly rising voltage
nodes, (switching nodes) and other noisy traces. The filter
capacitors C_FILTER1, C_FILTER2, and C_FILTER3 used in
conjunction with filter resistors R_FILTER1 and R_FILTER2 form
common mode and differential mode filters, as shown in
Figure 5. The noise environment of the application and
actual board layout conditions will drive the extent of filter
complexity. The maximum recommended resistance for
R_FILTER1 and R_FILTER2 is approximately 10Ω to avoid
interaction with the 50kΩ input resistance of the remote
sense differential amplifier. The physical location of these
resistors is not as critical as the filter capacitors. Typical
capacitance values for C_FILTER1, C_FILTER2, and C_FILTER3
range between 330pF to 1000pF and should be placed near
the IC.
VID<0:2>, OFFSET<0:1>, AF_EN, PGOOD, and
VR_ON
These are logic signals that do not require special attention.
FDE
This logic signal should be treated as noise sensitive and
should be routed away from rapidly rising voltage nodes,
(switching nodes) and other noisy traces.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It is
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application. An MLCC should be connected directly across
the drain of the high-side MOSFET and the source of the
low-side MOSFET to suppress turn-off voltage spikes.
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FN6753.1
July 8, 2010