ISL6263D Datasheet, PDF (13/17 Pages) Intersil Corporation – Pre-biased Output Start-Up Capability

ISL6263D
As an example, suppose an upper MOSFET has a gate
charge, Q_GATE, of 25nC at 5V and also assume the droop in
the drive voltage at the end of a PWM cycle is 200mV. One
will find that a bootstrap capacitance of at least 0.125µF is
required. The next larger standard value capacitance is
0.15µF. A good quality ceramic capacitor is recommended.
Soft-Start and Soft Dynamic VID Slew Rate
The output voltage of the converter tracks V_SOFT, the voltage
across the SOFT and VSS pins. As shown in Figure 1, the
SOFT pin is connected to the output of the VID DAC through
the unidirectional soft-start current source I_SS or the
bidirectional soft-dynamic VID current source I_DVID, and the
non-inverting input of the error amplifier. Current is sourced
from the SOFT pin when I_SS is active. The SOFT pin can both
source and sink current when I_DVID is active. The soft-start
capacitor C_SOFT changes voltage at a rate proportional to I_SS
or I_DVID. The ISL6263D automatically selects I_SS for the
soft-start sequence so that the in-rush current through the
output capacitors is maintained below the OCP threshold.
Once soft-start is complete, I_DVID is automatically selected for
output voltage changes commanded by the VID inputs,
charging C_SOFT when the output voltage is commanded to
rise, and discharging C_SOFT when the output voltage is
commanded to fall.
The GPU voltage regulator may require a minimum voltage
slew rate, which will be guaranteed by the value of C_SOFT.
For example, if the regulator requires 10mV/µs slew rate, the
value of C_SOFT can be calculated using Equation 4:
C_SOFT
= ^I--^D-----^V---^I--^D-----^--^m----ⁱ--ⁿ---^ =


1_----0_----m_-s----V_{-- }
1_----8_-1--0_-0---_-k---A_{-- =}
0.018  F
(EQ. 4)
I_DVID is the soft-dynamic VID current source, and its
minimum value is specified in the “Electrical Specifications”
table on page 6. Choosing the next lower standard
component value of 0.015µF will guarantee 10mV/µs slew
rate. This choice of C_SOFT controls the start-up slew-rate as
well. One should expect the output voltage during soft-start
to slew to the voltage commanded by the VID settings at a
nominal rate given by Equation 5:
d_----V_{-----Sd---O-t----F----T- = C-----S-}I_{--S-O---S-F----T-- = 0----.-40---2-1---5----A----F-- 2----.--8---m-s-----V--}
(EQ. 5)
Note that the slew rate is the average rate of change
between the initial and final voltage values.
It is worth it to mention that the surge current charges the
output capacitors when the output voltage is commanded to
rise. This surge current could be high enough to trigger the
OC protection circuit if the voltage slew rate is too high,
or/and the output capacitance is too large. The overcurrent
set point should guarantee the VID code transition
successful.
RBIAS Current Reference
The RBIAS pin is internally connected to a 1.55V reference
through a 3kΩ resistance. A bias current is established by
connecting a±1% tolerance, 150kΩ resistor between the
RBIAS and VSS pins. This bias current is mirrored, creating the
reference current I_OCSET that is sourced from the OCSET pin.
Do not connect any other components to this pin, as they will
have a negative impact on the performance of the IC.
Setting the PWM Switching Frequency
The R³ modulator scheme is not a fixed-frequency
architecture, lacking a fixed-frequency clock signal to produce
PWM. The switching frequency increases during the
application of a load to improve transient performance. The
static PWM frequency varies slightly depending on the input
voltage, output voltage and output current, but this variation is
normally less than 10% in continuous conduction mode.
Refer to Figure 2 and find that resistor R_FSET is connected
between the V W and COMP pins. A current is sourced from
VW through R_FSET creating the synthetic ripple window
voltage signal V_W, which determines the PWM switching
frequency. The relationship between the resistance of R_FSET
and the switching frequency in CCM is approximated by
Equation 6:
R_FSET = -^--^t-₄--–--₀---⁰⁰---^.--⁵_----^-₁---₀-¹---_–-⁰--₁-^–-₂--⁶----^
(EQ. 6)
t is the switching period. For example, the value of R_FSET for
300kHz operation is approximated using Equation 7:
7.110³ = -^--³---^.--³---³-----^---₄--¹-₀--⁰--₀--^–---_⁶----–₁----₀-⁰--_–-^.--⁵₁---₂-^-----¹----⁰---^–---⁶----^
(EQ. 7)
This relationship only applies to operation in constant
conduction mode because the PWM frequency naturally
decreases as the load decreases while in diode emulation
mode.
Inductor DCR Current Sense
ISL6263D provides the option of using the inductor DCR for
current sense. To maintain the current sense accuracy, an NTC
compensation network is optional when using DCR sense. The
process to compensate the DCR resistance variation takes
several iterative steps. Figure 2 shows the DCR sense method.
Figure 8 shows the simplified model of the current sense
circuitry. The inductor DC current I_O generates a DC voltage
drop on the inductor DCR. Equation 8 gives this relationship:
V_DCR = I_O  DCR
(EQ. 8)
An R-C network senses the voltage across the inductor to
get the inductor current information. R_N represents the
equivalent resistance of R_p and the optional NTC network
consisting of R_NTC and R_NTCS. R_N is temperature T
dependent and is given by Equation 9:
R_NT = ^--_R-^R----_NN----_T-^T--_C-^C-----+-+----_RR----_N-^N---_T-^T---_C-^C---_S-^S----^_+---^--_R-^R----_P-^P--
(EQ. 9)
If the NTC network is not used, simply set R_N(T) = R_P.
13
FN6753.1
July 8, 2010