ISL6263D Datasheet, PDF (11/17 Pages) Intersil Corporation – Pre-biased Output Start-Up Capability

ISL6263D
conduction losses. Efficiency can be further improved with a
reduction of unnecessary switching losses by reducing the
PWM frequency. The PWM frequency is configured to
automatically make a step-reduction upon entering DEM by
forcing a step-increase of the window voltage V_W. The
characteristic PWM frequency reduction, coincident with
decreasing load, is accelerated by the step-increase of the
window voltage.
The converter will enter DEM after detecting three
consecutive PWM pulses with negative inductor current. The
negative inductor current is detected during the time that the
high-side MOSFET gate driver output UGATE is low, with the
exception of a brief blanking period. The voltage between
the PHASE pin and VSS pin is monitored by a comparator
that latches upon detection of positive phase voltage. The
converter will return to CCM after detecting three
consecutive PWM pulses with positive inductor current.
The inductor current is considered positive if the phase
comparator has not been latched while UGATE is low.
Because the switching frequency in DEM is a function of load
current, very light load condition can produce frequencies well
into the audio band. To eliminate this audible noise, an audio
filter can be enabled that briefly turns on the low-side
MOSFET gate driver LGATE approximately every 35µs.
The DEM and audio filter operation are programmed by the
AF_EN and FDE pins according to Table 2.
TABLE 2. DIODE-EMULATION MODE AND AUDIO-FILTER
FDE
AF_EN
DEM STATUS
AUDIO
FILTER
0
0
0
1
Forced CCM
1
0
Enabled
Disabled
1
1
Enabled
Enabled
Smooth mode transitions are facilitated by the R³ modulator,
which correctly maintains the internally synthesized ripple
current information throughout mode transitions.
Current Monitor
The ISL6263D features a current monitor output. The
voltage between the IMON and VSS pins is proportional to
the output inductor current. The output inductor current is
proportional to the voltage between the ICOMP and VO pins.
The IMON pin has source and sink capability for close
tracking of transient current events. The current monitor
output is expressed in Equation 1:
V_IMON = V_ICOMP – V_O  31
(EQ. 1)
Protection
The ISL6263D provides overcurrent protection (OCP),
overvoltage protection (OVP), and undervoltage protection
(UVP), as shown in Table 3.
Overcurrent protection is tied to the current sense amplifier.
Given the overcurrent set point I_OC, the maximum voltage at
ICOMP pin V_ICOMP(max) (which is the voltage when OCP
happens) can be determined by the current sense network
(explained in “Inductor DCR Current Sense” on page 13 and
“Resistor Current Sense” on page 14). During start-up, the
ICOMP pin must fall 25mV below the OCSET pin to reset the
overcurrent comparator, which requires (V_ICOMP(max) - V_O)
> 25mV.
The OCP threshold detector is checked every 15µs and will
increment a counter if the OCP threshold is exceeded;
conversely the counter will be decremented if the load
current is below the OCP threshold. The counter will latch an
OCP fault when the counter reaches eight. The fastest OCP
response for overcurrent levels that are no more than 2.5x
the OCP threshold is 120µs, which is eight counts at 15µs
each. The ISL6263D protects against hard shorts by latching
an OCP fault within 2µs for overcurrent levels exceeding
2.5x the OCP threshold.
The overcurrent threshold is determined by the resistor
R_OCSET between OCSET pin and VO pin. The value of
R_OCSET is calculated in Equation 2:
R_OCSET = -^V----^I--^C----^O----^M----₁-^P---₀-^--^m-_---_A-^a---^x---^---–-----^V----^O---
(EQ. 2)
For example, choose V_ICOMP(max) - V_O = 80mV, R_OCSET
can use a 8.06kΩresistor, according to Equation 2.
Undervoltage protection is independent of the overcurrent
protection. If the output voltage measured on the VO pin is
less than +300mV below the voltage on the SOFT pin for
longer than 1ms, the controller will latch a UVP fault. If the
output voltage measured on the VO pin is greater than
195mV above the voltage on the SOFT pin for longer than
1ms, the controller will latch an OVP fault. Keep in mind that
V_SOFT will equal the voltage level commanded by the VID
states only after the soft-start capacitor C_SOFT has slewed to
the VID DAC output voltage. The UVP and OVP detection
circuits act on static and dynamic V_SOFT voltage.
When an OCP, OVP, or UVP fault has been latched, PGOOD
becomes a low impedance and the gate driver outputs
UGATE and LGATE are pulled low. The energy stored in the
inductor is dissipated as current flows through the low-side
MOSFET body diode. The controller will remain latched in
the fault state until the VR_ON pin has been pulled below the
falling VR_ON threshold voltage V_{VR_ONL} or until VDD has
gone below the falling POR threshold voltage ^V_{VDD_THF}.
A severe-overvoltage protection fault occurs immediately after
the voltage between the VO and VSS pins exceed the rising
severe-overvoltage threshold V_OVPS, which is 1.55V. The
ISL6263D will latch UGATE and PGOOD low but unlike other
protective faults, LGATE remains high until the voltage
between VO and VSS falls below approximately 0.76V, at
which time LGATE is pulled low. The LGATE pin will continue
to switch high and low at 1.55V and 0.76V until VDD has gone
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FN6753.1
July 8, 2010