ISL6263D Datasheet, PDF (15/17 Pages) Intersil Corporation – Pre-biased Output Start-Up Capability

ISL6263D
actual inductor current information, R_S and C_N simply provide
noise filtering. A low ESL sense resistor is strongly
recommended for R_SNS because this parameter is the most
significant source of noise that affects discrete resistor sense.
It is recommended to start out using 100Ω for R_S and 47pF for
C_N. Since the current sense resistance changes very little
with temperature, the NTC network is not needed for thermal
compensation. Discrete resistor sense design follows the
same approach as inductor DCR sense. The voltage on the
current sense resistor is given by Equation 20:
V_RSNS = I_O  R_SNS
(EQ. 20)
It is optional to parallel a resistor R_P to form a voltage divider
with R_S to obtain more flexibility. Assume the voltage across
R_P is V_N, which is given by Equation 21:
V_N = V_RSNS  _R-----_S---^R--+--^P---_R-----_P-
(EQ. 21)
The current sense amplifier output voltage V_ICOMP is given
by Equation 22:
V_ICOMP
=
V_O
+
V_N




1
+
R^{-R----II--SS----21-}_{}
(EQ. 22)
Given a current sense resistor R_SNS and the overcurrent set
point I_OC, the maximum voltage of ICOMP pin is determined
by Equation 23:
V_{ICOMPmax} – V_O
=
I_OC

R_SNS

-_R----_S---^R--+--^P---_R-----_P-



1

+
R^{-R----II--SS----21-}_{}
(EQ. 23)
Given the output current I_O, the current monitor IMON
voltage can be determined by Equation 24:
V_IMON
=
31

I_O

R_S
N
S

-_R----_S---^R--+--^P---_R-----_P-

 1

+
R^{-R----II--SS----21-}_{}
(EQ. 24)
If R_P is not used, the maximum voltage of ICOMP pin is
determined by Equation 25:
V_{ICOMPmax} – V_O
=
I_O
C

R_S
N
S




1
+
R^{-R----II--SS----21-}_{}
(EQ. 25)
VDD
and given the output current I_O, the IMON voltage is
determined by Equation 26:
V_IMON
=
31

I_O

R_SN
S




1
+
RR_{-----II--SS----21-}
(EQ. 26)
R_S, R_P, R_IS1, R_IS2 should be adjusted to meet the
requirement (V_ICOMP(max) - V_O) > 25mV.
The current sense traces should be routed directly to the
current sense resistor pads for accurate measurement.
However, due to layout imperfection, the calculated R_IS2
may still need slight adjustment to achieve optimum load line
slope. It is recommended to adjust R_IS2 after the system has
achieved thermal equilibrium at full load.
Dynamic Mode of Operation - Compensation
Parameters
Intersil provides a spreadsheet to calculate the compensator
parameters. Caution needs to be used in choosing the input
resistor to the FB pin. Excessively high resistance will cause
an error to the output voltage regulation due to the bias
current flowing through the FB pin. It is recommended to
keep this resistor below 3kΩ.
Layout Considerations
As a general rule, power should be on the bottom layer of
the PCB and weak analog or logic signals are on the top
layer of the PCB. The ground-plane layer should be adjacent
to the top layer to provide shielding.
Inductor Current Sense and the NTC Placement
It is crucial that the inductor current be sensed directly at the
PCB pads of the sense element, be it DCR sensed or discrete
resistor sensed. The effect of the NTC on the inductor DCR
thermal drift is directly proportional to its thermal coupling with
the inductor and thus, the physical proximity to it.
Signal Ground and Power Ground
The ground plane layer should have a single point connection
to the analog ground at the VSS pin. The VSS island should
be located under the IC package along with the weak analog
-
OCP
+
+
-
10A _
OCSET
ISP
+
Isense
-
ISN
ICOMP
VO
R_OCSET
R_S
R_P
(optional)
V_RSNS
FIGURE 9. EQUIVALENT MODEL OF CURRENT SENSE USING DISCRETE RESISTOR CURRENT SENSE
15
FN6753.1
July 8, 2010