ISL6263D Datasheet, PDF (12/17 Pages) Intersil Corporation – Pre-biased Output Start-Up Capability

ISL6263D
below the falling POR threshold voltage ^V_{VDD_THF.} This
provides maximum protection against a shorted high-side
MOSFET while preventing the output voltage from ringing
below ground. The severe-overvoltage fault circuit can be
triggered after another fault has already been latched.
Gate-Driver Outputs LGATE and UGATE
The ISL6263D has internal high-side and low-side
N-Channel MOSFET gate-drivers. The LGATE driver is
optimized for low duty-cycle applications where the low-side
MOSFET conduction losses are dominant. The LGATE
pull-down resistance is very low in order to clamp the
gate-source voltage of the MOSFET below the V_GS(th) at
turn-off. The current transient through the low-side gate at
turn-off can be considerable due to the characteristic large
switching charge of a low r_DS(ON) MOSFET.
PWM
LGATE
1V
UGATE
1V
across the BOOT and PHASE pins. The boot capacitor is
charged from PVCC through an internal bootstrap diode
each time the low-side MOSFET turns on, pulling the
PHASE pin low.
Internal Bootstrap Diode
The ISL6263D has an integrated boot-strap Schottky diode
connected from the PVCC pin to the BOOT pin. Simply adding
an external capacitor across the BOOT and PHASE pins
completes the bootstrap circuit.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
Q_GATE = 100nC
0.4
0.2 _20nC
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
V_{BOOT_CAP} (V)
FIGURE 7. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
t _PDRU
t _PDRL
FIGURE 6. GATE DRIVER TIMING DIAGRAM
Adaptive shoot-through protection prevents the gate-driver
outputs from going high until the opposite gate-driver output
has fallen below approximately 1V. The UGATE turn-on
propagation delay t_PDRU and LGATE turn-on propagation
delay t_PDRL are found in the “Electrical Specifications” table
on page 6. The power for the LGATE gate-driver is sourced
directly from the PVCC pin. The power for the UGATE
gate-driver is sourced from a bootstrap capacitor connected
The minimum value of the bootstrap capacitor can be
calculated using Equation 3:
C_BOOT  _---^Q--_V--^G--_B---^A-_O---^T-_O--^E---_T-
(EQ. 3)
where Q_GATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The V_BOOT term is
defined as the allowable droop in the rail of the upper drive.
FAULT TYPE
Overcurrent
Short Circuit
Overvoltage (+195mV) between VO
pin and SOFT pin
Severe Overvoltage (+1.55V) between
VO pin and VSS pin
Undervoltage (-300mV) between VO
pin and SOFT pin
TABLE 3. FAULT PROTECTION SUMMARY OF ISL6263D
FAULT DURATION
PRIOR TO PROTECTION
PROTECTION ACTIONS
120µs
LGATE, UGATE, and PGOOD latched low
<2µs
LGATE, UGATE, and PGOOD latched low
1ms
LGATE, UGATE, and PGOOD latched low
Immediately
1ms
UGATE, and PGOOD latched low, LGATE
toggles ON when VO>1.55V OFF when VO
<0.76V until fault reset
LGATE, UGATE, and PGOOD latched low
FAULT RESET
Cycle VR_ON or VDD
Cycle VR_ON or VDD
Cycle VR_ON or VDD
Cycle VDD only
Cycle VR_ON or VDD
12
FN6753.1
July 8, 2010