ISL6563 Datasheet, PDF (15/19 Pages) Intersil Corporation – Two-Phase Multiphase Buck PWM Controller with Integrated MOSFET Drivers

ISL6563
The feedback resistor, R₁, has already been chosen as
outlined in “Load Line Regulation Resistor” on page 14.
Select a target bandwidth for the compensated system, f₀.
The target bandwidth must be large enough to ensure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency (75kHz in this case). The
values of the compensation components depend on the
relationships of f₀ to the output filter, LC, double pole
frequency and the ESR zero frequency of the bulk output
capacitor bank. For each of the three cases defined in the
following, there is a separate set of equations for the
compensation components.
Case 1:
-----------¹------------
2π ⋅ LC
>
f₀
R₂
=
R₁
⋅
-²---^π-----^â‹---^f--⁰----^â‹---^V-----^P----^P-----^â‹-------^L----^C--
0.66 ⋅ V_IN
C₂
=
------------⁰---^.--⁶---⁶-----^â‹---^V----^I--^N--------------
2π ⋅ V_PP ⋅ R_FB ⋅ f₀
(EQ. 18)
Case 2:
-----------¹------------
2π ⋅ LC
≤
f₀
≤
2^----π^-----⋅^---C^----1--⋅^---E^----S^-----R^---
R₂
=
R₁
⋅
-^V----^P----^P-----^â‹---⁽--²----^π----⁾--²----^â‹---^f--⁰²-----^â‹---^L---^C---
0.66 ⋅ V_IN
C₂
=
----------------------⁰---^.--⁶----⁶----^â‹---^V-----^I-^N------------------------
(2π)² ⋅ f₀₂ ⋅ V_PP ⋅ R₁ ⋅ LC
(EQ. 19)
Case 3:
f₀
>
----------------¹-----------------
2π ⋅ C ⋅ ESR
R₂
=
R₁
⋅
--²----^π-----^â‹---^f--⁰----^â‹---^V----^P----^P-----^â‹---^L----
0.66 ⋅ V_IN ⋅ ESR
(EQ. 20)
C₂
=
0_----._--6_---6_-----⋅_---V_{----I--N-----}⋅_---E_-----S_----R_------⋅_-------C_---
2π ⋅ V_PP ⋅ R₁ ⋅ f₀ ⋅ L
In the previous equations, L is the per-channel filter
inductance divided by the number of active channels, C is
the total bulk output capacitance, ESR is the equivalent
series resistance of the bulk output filter capacitance, and
V_PP is the peak-to-peak sawtooth signal amplitude (see
“Electrical Specifications” table on page 4).
Once selected, the compensation values assure a stable
converter with reasonable transient performance. C₁ is
needed to cut down the high frequency error amplifier gain
and reduce the noise the PWM comparator sees. Keep a
position available for C₁, and install a 10pF to 47pF in case
jitter is noted.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
square wave voltage at the phase nodes. Additionally, the
output capacitors must also provide the energy required by a
fast transient load during the short interval of time required
by the controller and power train to respond. Because it has
a low bandwidth compared to the switching frequency, the
output filter limits the system transient response leaving the
output capacitor bank to supply the load current or sink the
inductor currents, all while the current in the output inductors
increases or decreases to meet the load demand.
In high-speed converters, the output capacitor bank is
amongst the costlier (and often the physically largest) parts
of the circuit. Output filter design begins with consideration
of the critical load parameters: maximum size of the load
step, ΔI, the load-current slew rate, di/dt, and the maximum
allowable output voltage deviation under transient loading,
ΔV_MAX. Capacitors are characterized according to their
capacitance, ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output-
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates according to
Equation 21:
Δ
V
≈
(ESL
)
-^d---ⁱ
dt
+
(
ESR)
ΔI
(EQ. 21)
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔV_MAX.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors is also responsible for the
majority of the output-voltage ripple. As the bulk capacitors
sink and source the inductor ac ripple current, a voltage
develops across the bulk-capacitor ESR equal to I_PP. Thus,
once the output capacitors are selected and a maximum
allowable ripple voltage, V_PP(MAX), is determined from an
analysis of the available output voltage budget, Equation 22
can be used to determine a lower limit on the output
inductance.
L ≥ ESR ⋅ ⁽---^V----_f^I--_SN-----_â‹^–---_V--²--_I--_N-^â‹---^V-_â‹---^O_V----_PU----_P-^T---₍⁾--_M--^â‹---^V_A----_XO----₎^U-----^T-
(EQ. 22)
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
15
FN9126.8
June 10, 2010