ISL6563 Datasheet, PDF (14/19 Pages) Intersil Corporation – Two-Phase Multiphase Buck PWM Controller with Integrated MOSFET Drivers

ISL6563
The above equation assumes the current through the lower
MOSFET is always positive; if so, the total power dissipated
in each lower MOSFET is approximated by the summation of
P_LMOS1 and P_LMOS2.
UPPER MOSFET POWER CALCULATION
In addition to r_DS(ON) losses, a large portion of the upper-
MOSFET losses are switching losses, due to currents
conducted through the device while the input voltage is
present as V_DS. Upper MOSFET losses can be divided into
separate components, separating the upper-MOSFET
switching losses, the lower-MOSFET body diode reverse
recovery charge loss, and the upper MOSFET r_DS(ON)
conduction loss.
In most typical circuits, when the upper MOSFET turns off, it
continues to conduct the inductor current until the voltage at
the phase node falls below ground. Once the lower
MOSFET begins conducting (via its body diode or
enhancement channel), the current in the upper MOSFET
falls to zero. In Equation 12, the required time for this
commutation is t₁and the associated power loss is P_UMOS,1.
P _{U M O S ,1}
≈
V_IN
⎛
⎜
-^I-^O-----^U----^T--
⎝²
+
I_{--L----,-P----P--⎟⎞}
2_⎠
⎛
⎜
⎝
-^t-¹--
2
⎞
⎟
⎠
f_S
(EQ. 12)
Similarly, the upper MOSFET begins conducting as soon as
it begins turning on. Assuming the inductor current is in the
positive domain, the upper MOSFET sees approximately the
input voltage applied across its drain and source terminals,
while it turns on and starts conducting the inductor current.
This transition occurs over a time t₂, and the approximate
the power loss is P_UMOS,2.
P_{UMOS, 2}
≈
V_IN
⎛
⎜
-^I-^O-----^U----^T--
⎝²
–
-^I-^L----^,-^P----^P--⎟⎞
2_⎠
⎛
⎜
⎝
t_--2--
⎞
⎟
2_⎠
f_S
(EQ. 13)
A third component involves the lower MOSFET’s reverse-
recovery charge, Q_RR. Since the lower MOSFET’s body
diode conducts the full inductor current before it has fully
switched to the upper MOSFET, the upper MOSFET has to
provide the charge required to turn off the lower MOSFET’s
body diode. This charge is conducted through the upper
MOSFET across VIN, the power dissipated as a result,
P_UMOS,3 can be approximated using Equation 14:
P_UMOS,3 = V_IN Q_rr f_S
(EQ. 14)
Lastly, the conduction loss part of the upper MOSFET’s
power dissipation, P_UMOS,4, can be calculated using
Equation 15:
P _{U M O S ,4}
=
r_DS(ON)
⎛
⎜
⎝
-^I-^O-----^U----^T--⎟⎞
2⎠
2
d
+
-^I-^P----^P--²-
12
(EQ. 15)
In this case, of course, r_DS(ON) is the ON-resistance of the
upper MOSFET.
The total power dissipated by the upper MOSFET at full load
can be approximated as the summation of these results.
Since the power equations depend on MOSFET parameters,
choosing the correct MOSFETs can be an iterative process
that involves repetitively solving the loss equations for
different MOSFETs and different switching frequencies until
converging upon the best solution.
Current Sensing
The resistor connected between the ISEN and VCC pins
determines the gain in the load-line regulation and the
channel-current balance loop. Select the value for this
resistor based on the room temperature r_DS(ON) of the lower
MOSFETs and the full-load total output current, I_FL.
R_ISEN
=
5^-r--D-0^---S--×^--(-1^-O--0^{---N-–--6-)-}
⋅
-^I-^F----^L-
2
(EQ. 16)
Load Line Regulation Resistor
The load-line regulation resistor is labeled, R1 in Figure 1,
depends on the desired full-load droop voltage. At full load,
the current determined by R_ISEN is fed into the FB pin and
creates the output voltage droop across R1. Thus, the load
line regulation resistor can be computed using Equation 17:
R₁ = -^V----^D----^R-_r---_DO----_S-^O---₍-^P-_O----^â‹_N---²--₎---_⋅â‹---_IR--_F---^IL-^S----^E----^N--
(EQ. 17)
Frequency Compensation
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output filter LC resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R₂ and C₂.
The solution to the system equations can be fairly
complicated. Fortunately, there is a simple approximation
that comes very close to an optimal solution. Treating the
system as though it were a voltage mode regulator by
compensating the LC poles and the ESR zero of the voltage
mode approximation yields a solution that is always stable
with very close to ideal transient performance.
C₁
R₂
C₂
COMP
FB
+
R_{1 VDROOP}
-
V_OUT
FIGURE 8. COMPENSATION CONFIGURATION FOR ISL6563
CIRCUIT
14
FN9126.8
June 10, 2010