ISL6563 Datasheet, PDF (13/19 Pages) Intersil Corporation – Two-Phase Multiphase Buck PWM Controller with Integrated MOSFET Drivers

ISL6563
schematic in Figure 6 demonstrates coordination of the
ISL6563 with such a rail; the resistor components are
chosen to enable the ISL6563 as the 12V input exceeds
approximately 9.75V. Additionally, an open-drain or open-
collector device can be used to wire-AND a second (or
multiple) control signal, as shown in Figure 6. To defeat the
threshold-sensitive enable, connect ENLL to VCC directly or
via a pull-up resistor.
The ‘11111’ VID code is reserved as a signal to the controller
that no load is present. The controller is disabled while
receiving this VID code and will subsequently start up upon
receiving any other code.
In summary, for the ISL6563 to operate, the following
conditions need be met: VCC and PVCC must be greater
than their respective POR thresholds, the voltage at ENLL
must be greater than 0.61V, and VID has to be different than
‘11111’. Once all these conditions are met, the controller
immediately initiates a soft start sequence.
SOFT-START
The soft-start function allows the converter to bring up the
output voltage in a controlled fashion, resulting in a linear
ramp-up. Following a delay of 16 PHASE clock cycles (about
70μs) between enabling the chip and the start of the ramp,
the output voltage progresses at a fixed rate of 12.5mV per
16 PHASE clock cycles.
Thus, the soft-start period (not including the 70µs wait) up to
a given voltage, V_DAC, can be approximated by Equation 9:
T_SS
=
V_{-----D----A----C-----}⋅_---1_---2_----8_---0_--
f_S
(EQ. 9)
where V_DAC is the DAC-set VID voltage, and f_S is the
switching frequency (typically 222kHz).
The ISL6563 also has the ability to start up into a pre-charged
output, without causing any unnecessary disturbance. The FB
pin is monitored during soft-start, and should it be higher than
the equivalent internal ramping reference voltage, the output
drives hold both MOSFETs off. Once the internal ramping
reference exceeds the FB pin potential, the output drives are
enabled, allowing the output to ramp from the pre-charged level
to the final level dictated by the DAC setting. Should the output
be pre-charged to a level exceeding the DAC setting, the output
drives are enabled at the end of the soft-start period, leading to
an abrupt correction in the output voltage down to the DAC-set
level.
General Application Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multiphase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and
example board layouts for all common microprocessor
applications.
OUTPUT PRECHARGED
ABOVE DAC LEVEL
OUTPUT PRECHARGED
BELOW DAC LEVEL
GND>
V_OUT (0.5V/DIV)
GND>
ENLL (5V/DIV)
T1 T2
T3
FIGURE 7. SOFT-START WAVEFORMS FOR ISL6563-BASED
MULTIPHASE CONVERTER
MOSFETs
Given the fixed switching frequency of the ISL6563 and the
integrated output drives, the selection of MOSFETs revolves
closely around the current each MOSFET is required to
conduct, the capability of the devices to dissipate heat, as well
as the characteristics of available heat sinking. Since the
ISL6563 drives the MOSFETs with 5V, the selection of
appropriate MOSFETs should be done by comparing and
evaluating their characteristics at this specific V_GS bias
voltage.
LOWER MOSFET POWER CALCULATION
Since virtually all of the heat loss in the lower MOSFET is
conduction loss (due to current conducted through the channel
resistance, r_DS(ON)), a quick approximation for heat dissipated
in the lower MOSFET can be found in Equation 10:
P_LMOS1
=
r_DS(ON)
⎛
⎜
-^I-^O-----^U----^T--⎟⎞
⎝ 2⎠
2
(1
–
D)
+
-^I-^L----^,-^P----^P2----⁽--¹-----–-----^D-----⁾
12
(EQ. 10)
where: I_M is the maximum continuous output current, I_L,PP is
the peak-to-peak inductor current, and D is the duty cycle
(approximately V_OUT/V_IN).
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I_M, V_D(ON); the switching
frequency, f_S; and the length of dead times, t_d1 and t_d2, at
the beginning and the end of the lower-MOSFET conduction
interval, respectively.
P_{LMOS 2}
=
V_D(ON) f_S
⎛
⎜
-^I-^O-----^U----^T--
⎝2
+
I_{--P----P--⎟⎞}
2⎠
t_d1
+
⎛
⎜
-^I-^O-----^U----^T--
⎝2
–
I_{--P----P--⎟⎞}
2⎠
t_d2
(EQ. 11)
13
FN9126.8
June 10, 2010