ISL6563 Datasheet, PDF (12/19 Pages) Intersil Corporation – Two-Phase Multiphase Buck PWM Controller with Integrated MOSFET Drivers

ISL6563
In VRM10 setting, the ISL6563 checks for a change in the VID
code six times each switching cycle. If a new code is
established and it stays the same for 3 consecutive readings,
the ISL6563 recognizes the change and increments the
reference. Specific to VRM10, the processor controls the VID
transitions and is responsible for incrementing or decrementing
one VID step at a time. In VRM10 setting, the ISL6563 will
immediately change the reference to the new requested value
as soon as the request is validated; in cases where the
reference step is too large, the sudden change can trigger
overcurrent or overvoltage events.
In non-VRM10 settings, due to the way the ISL6563
recognizes VID code changes, up to one full switching
period may pass before a VID change registers. Thus, the
total time required for a VID change, t_DVID, is dependent on
the switching frequency (f_S), the size of the change (ΔV_ID),
and the time required to register the VID change. The
approximate time required for an ISL6563-based converter
in VRM9 configuration running at typical f_S (222kHz) to
perform a 1.5V-to-1.7V reference voltage change is about
196μs, as calculated using Equation 7 (this example is also
illustrated in Figure 5).
t_DVID
≅
--¹--
f_S
⎛
⎜
⎝
-⁴---^Δ----^V----^V----^I--^D--
0.025
⎞
+ 13⎟
⎠
(EQ. 7)
OVERVOLTAGE PROTECTION
The ISL6563 benefits from a multi-tiered approach to
overvoltage protection.
A pre-POR mechanism is at work while the chip does not
have sufficient bias voltage to initiate an active response to
an OV situation. Thus, while VCC is below its POR level, the
lower drives are tristated and internal 5kΩ (typically)
resistors are connected from PHASE to their respective
LGATE pins. As a result, output voltage, duplicated at the
PHASE nodes via the output inductors, is effectively
clamped at the lower MOSFETs’ threshold level. This
approach ensures no catastrophic output voltage can be
developed at the output of an ISL6563-based regulator (for
most typical applications).
The pre-POR mechanism is removed once the bias is above
the POR level, and a fixed-threshold OVP goes into effect.
Based on the specific chip configuration, the OVP goes into
effect once the voltage sensed at the FB pin exceeds about
1.65V (Hammer/VR10) or 1.95V (VR9 configuration). Should
the output voltage exceed these thresholds, the lower
MOSFETs are turned on.
During soft-start, the OVP threshold changes to the higher of
the fixed threshold (1.65V/1.95V) or the DAC setting plus
200mV. At the end of the soft-start, the OVP threshold
changes to the DAC setting plus 200mV.
In any of the described post-POR functionality, OVP results
in the turn-on of the lower MOSFETs. Once turned on, the
lower MOSFETs are only turned off when the output voltage
drops below the OV comparator’s hysteretic threshold. The
OVP process repeats if the voltage rises back above the
designated threshold. The occurrence of an OVP event does
not latch the controller; should the phenomenon be
transitory, the controller resumes normal operation following
such an event.
LOAD-LINE REGULATION
In applications with high transient current slew rates, the
lowest-cost solution for maintaining regulation often requires
some kind of controlled output impedance. The FB pin of the
ISL6563 carries a current proportional to the average output
current of the converter. The current is equivalent to I_FB in
Figure 1. Forcing I_FB into the summing node of the error
amplifier produces a voltage drop across the feedback resistor,
R_FB, proportional to the output current. Assuming the current is
shared equally by both phases, the steady-state value of
V_DROOP is simply:
V_DROOP = I_FB ⋅ R_FB
V_DROOP = ^I--^O-----^U----^T-----^â‹₂---^r--^D_â‹---_R-^S----_I⁽--_SO----_E-^N--_N--⁾--^L---^M-----^O-----^S-- ⋅ R_FB
(EQ. 8)
ON/OFF CONTROL
The internal power-on reset circuit (POR) prevents the
ISL6563 from starting before the bias voltage at VCC and
PVCC reach the rising POR thresholds, as defined in
“Electrical Specifications” table on page 4. The POR levels
are sufficiently high to guarantee that all parts of the ISL6563
can perform their functions properly once bias is applied to
the part. While bias is below the rising POR thresholds, the
controlled MOSFETs are kept in an off state.
ISL6563
EXTERNAL CIRCUIT
+5V
+12V
POR
CIRCUIT
ENABLE
COMPARATOR
+
-
VCC
15kΩ
ENLL
1kΩ
0.61V
OFF
ON
FIGURE 6. START-UP COORDINATION USING THRESHOLD-
SENSITIVE ENABLE (ENLL) PIN
A secondary disablement feature is available via the
threshold-sensitive enable input (ENLL). This optional
feature prevents the ISL6563 from operating until a certain
other voltage rail is available and above some selectable
threshold. For example, when down-converting off a 12V
input, it may be desirable the ISL6563-based converter does
not start up until the power input is sufficiently high. The
12
FN9126.8
June 10, 2010