ISL6406_07 Datasheet, PDF (14/18 Pages) Intersil Corporation – Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

ISL6406
Given the reduced available gate bias voltage (5V), logic-
level or sub-logic-level transistors should be used for both
N-MOSFETs. Caution should be exercised with devices
exhibiting very low V_GS(ON) characteristics. The shoot-
through protection present aboard the ISL6406 may be
circumvented by these MOSFETs if they have large parasitic
impedances and/or capacitances that would inhibit the gate
of the MOSFET from being discharged below its threshold
level before the complementary MOSFET is turned on.
Bootstrap Component Selection
External bootstrap components, a diode and capacitor, are
required to provide sufficient gate enhancement to the upper
MOSFET. The internal MOSFET gate driver is supplied by
the external bootstrap circuitry as shown in Figure 9. The
boot capacitor, C_BOOT, develops a floating supply voltage
referenced to the PHASE pin. This supply is refreshed each
cycle, when D_BOOT conducts, to a voltage of CPVOUT less
the boot diode drop, V_D, plus the voltage rise across
Q_LOWER.
ISL6406
CPVOUT
D_{BOOT +}
V_D
V_IN
-
BOOT
C_BOOT
UGATE
PHASE
Q_UPPER
NOTE:
V_G-S = V_CC -V_D
-
LGATE
Q_LOWER
+
GND
NOTE:
V_G-S = V_CC
FIGURE 9. UPPER GATE DRIVE BOOTSTRAP
Just after the PWM switching cycle begins and the charge
transfer from the bootstrap capacitor to the gate capacitance
is complete, the voltage on the bootstrap capacitor is at its
lowest point during the switching cycle. The charge lost on
the bootstrap capacitor will be equal to the charge
transferred to the equivalent gate-source capacitance of the
upper MOSFET as shown:
Q_GATE = C_BOOT × (V_BOOT1 – V_BOOT2)
(EQ. 13)
where Q_GATE is the maximum total gate charge of the upper
MOSFET, C_BOOT is the bootstrap capacitance, V_BOOT1 is
the bootstrap voltage immediately before turn-on, and
V_BOOT2 is the bootstrap voltage immediately after turn-on.
The bootstrap capacitor begins its refresh cycle when the gate
drive begins to turn-off the upper MOSFET. A refresh cycle
ends when the upper MOSFET is turned on again, which
varies depending on the switching frequency and duty cycle.
The minimum bootstrap capacitance can be calculated by
rearranging Equation 13 and solving for C_BOOT.
C_BOOT
=
-----------------Q-----^G----^A----^T----^E------------------
V_BOOT1 – V_BOOT2
(EQ. 14)
Typical gate charge values for MOSFETs considered in
these types of applications range from 20nC to 100nC.
Since the voltage drop across Q_LOWER is negligible,
V_BOOT1 is simply V_CPVOUT - V_D. A schottky diode is
recommended to minimize the voltage drop across the
bootstrap capacitor during the on-time of the upper
MOSFET. Initial calculations with V_BOOT2 no less than 4V
will quickly help narrow the bootstrap capacitor range.
For example, consider an upper MOSFET is chosen with a
maximum gate charge, Q_g, of 100nC. Limiting the voltage
drop across the bootstrap capacitor to 1V results in a value
of no less than 0.1μF. The tolerance of the ceramic capacitor
should also be considered when selecting the final bootstrap
capacitance value.
A fast recovery diode is recommended when selecting a
bootstrap diode to reduce the impact of reverse recovery
charge loss. Otherwise, the recovery charge, Q_RR, would
have to be added to the gate charge of the MOSFET and
taken into consideration when calculating the minimum
bootstrap capacitance.
14
FN9073.7
January 16, 2007