ISL6406_07 Datasheet, PDF (11/18 Pages) Intersil Corporation – Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

ISL6406
converter. Note that capacitors C_IN and C_OUT could each
represent numerous physical capacitors.
Dedicate one solid layer, usually a middle layer of the PC
board, for a ground plane and make all critical component
ground connections with vias to this layer. Dedicate another
solid layer as a power plane and break this plane into
smaller islands of common voltage levels. Keep the metal
runs from the PHASE terminals to the output inductor short.
The power plane should support the input power and output
power nodes. Use copper-filled polygons on the top and
bottom circuit layers for the phase nodes. Use the remaining
printed circuit layers for small signal wiring. The wiring traces
from the GATE pins to the MOSFET gates should be kept
short and wide enough to easily handle the 1A of drive
current. The switching components should be placed close
to the ISL6406 first. Minimize the length of the connections
between the input capacitors, C_IN, and the power switches
by placing them nearby. Position both the ceramic and bulk
input capacitors as close to the upper MOSFET drain and
islands as possible. Position the output inductor and output
capacitors between the upper and lower MOSFETs and the
load.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Position the bypass capacitor, C_BP, close to
the VCC pin with a via directly to the ground plane. Place
the PWM converter compensation components close to the
FB and COMP pins. The feedback resistors for both
regulators should also be located as close as possible to
the relevant FB pin with vias tied straight to the ground
plane as required.
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V_OUT) is regulated to the Reference voltage level. The error
amplifier (Error Amp) output (V_E/A) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with a peak amplitude of V_IN at the
PHASE node. The PWM wave is smoothed by the output
filter (L and C_O).The modulator transfer function is the
small-signal transfer function of V_OUT/V_E/A. This function is
dominated by a DC Gain and the output filter (L_O and C_O),
with a double pole break frequency at F_LC and a zero at
F_ESR. The DC Gain of the modulator is simply the input
voltage (V_IN) divided by the peak-to-peak oscillator voltage,
V_OSC.
OSC
PWM
COMPARATOR
-
Δ V_OSC
+
DRIVER
DRIVER
V_IN
L_O
PHASE _CO
V_OUT
Z_FB
V_E/A
-
Z_IN
+
ERROR ^REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C₁
C₂
R₂
Z_FB
V_OUT
Z_IN
C₃ R₃
COMP
-
+
R₁
FB
ISL6406 REFERENCE
FIGURE 7. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
f_LC
=
--------------1---------------
2Π L_OC_O
(EQ. 4)
f_ESR
=
-------------------1---------------------
2Π(ESR)(C_O)
(EQ. 5)
The compensation network consists of the error amplifier
(internal to the ISL6406) and the impedance networks Z_IN
and Z_FB.The goal of the compensation network is to provide
a closed-loop transfer function with the highest 0dB crossing
frequency (f 0dB ) and adequate phase margin. Phase
margin is the difference between the closed loop phase at
f 0dB and 180°.
The equations below relate the compensation network’s
poles, zeros and gain to the components (R₁, R₂, R₃, C₁, C₂
and C₃) in Figure 7. Use these guidelines for locating the
poles and zeros of the compensation network:
1. Pick gain (R₂/R₁) for desired converter bandwidth.
2. Place first zero below filter’s double pole (~75% F_LC).
3. Place second zero at filter’s double pole.
4. Place first pole at the ESR zero.
5. Place second pole at half the switching frequency.
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin—repeat if necessary.
11
FN9073.7
January 16, 2007