ISL6406_07 Datasheet, PDF (13/18 Pages) Intersil Corporation – Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

ISL6406
ΔV_OUT = ΔI x ESR
(EQ. 8)
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6406 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. Equations 9 and
10 give the approximate response time interval for
application and removal of a transient load:
t_RISE =
L x I_TRAN
V_IN - V_OUT
(EQ. 9)
t_FALL =
L x I_TRAN
V_OUT
(EQ. 10)
where: I_TRAN is the transient load current step, t_RISE is the
response time to the application of load, and t_FALL is the
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q₁ turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q₁ and the source of Q₂.
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
The maximum RMS current required by the regulator may be
closely approximated through Equation 11:
I_RMSMAX =
V_{-----O----U---T-}
V_IN
×
⎛
⎝
I_O
U
2
TMAX
+
--¹----
12
×
⎛
⎝
-^V----^I-^N-----–-----^V----^O----^U---^T-
L × f_s
×
-^V--_V--^O--_I--^UN---^T-_⎠⎞
2_⎞
⎠
(EQ. 11)
For a through hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These capacitors
must be capable of handling the surge-current at power-up.
Some capacitor series available from reputable manufacturers
are surge current tested.
MOSFET Selection/Considerations
The ISL6406 requires two N-Channel power MOSFETs.
These should be selected based upon r_DS(ON), gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed between
the two MOSFETs according to duty factor.
The switching losses seen when sourcing current will be
different from the switching losses seen when sinking current.
When sourcing current, the upper MOSFET realizes most of
the switching losses. The lower switch realizes most of the
switching losses when the converter is sinking current (see
equations on next page). These equations assume linear
voltage-current transitions and do not adequately model power
loss due the reverse-recovery of the upper and lower
MOSFET’s body diode.
The gate-charge losses are dissipated by the ISL6406 and
don't heat the MOSFETs. However, large gate-charge
increases the switching interval, t_SW which increases the
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
Losses while Sourcing current
P_UPPER
=
I
o²
×
r_D
S
(
O
N
)
×
D
+
1_--
2
⋅
I
o
×
V_IN
×
t_S
W
×
f_s
P_LOWER = Io² x r_DS(ON) x (1 - D)
Losses while Sinking current
P_UPPER = Io² x r_DS(ON) x D
P_LOWER
=
I
o²
×
r_D
S
(ON)
×
(1
–
D)
+
1_--
2
⋅
Io
×
V_I
N
×
t_S
W
×
f_s
Where: D is the duty cycle = V_OUT / V_IN,
t_SW is the combined switch ON and OFF time, and
f_s is the switching frequency.
(EQ. 12)
13
FN9073.7
January 16, 2007