ISL6406_07 Datasheet, PDF (12/18 Pages) Intersil Corporation – Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

ISL6406
During overcurrent hiccup mode the COMP pin will rail HIGH
to about 5V. When the soft start sequence is initiated out of
hiccup mode the COMP pin will have to discharge from 5V to
about 1.2V, the beginning of the PWM ramp in order to start
up properly. Use of a small COMP to FB Rs and Cs as
possible is recommended. The recommended value for C2
in Figure 7 is 4700pF or less.
Compensation Break Frequency
Equations
Figure 8 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high
gain peak due to the high Q factor of the output filter and is
not shown in Figure 8. Using the above guidelines should
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F_P2 with the
capabilities of the error amplifier. The Closed Loop Gain is
constructed on the graph of Figure 8 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain. The compensation gain uses external impedance
networks Z_FB and Z_IN to provide a stable, high bandwidth
(BW) overall loop. A stable control loop has a gain crossing
with -20dB/decade slope and a phase margin greater than
45 degrees. Include worst-case component variations when
determining phase margin.
F_Z1
F_Z2 F_P1 F_P2
OPEN LOOP
100
ERROR AMP GAIN
80
20 log
⎛
⎜
⎝
V^----V-_O^---I-_S^-N---_C^--_{⎠⎟⎞}
60
40
COMPENSATION
GAIN
20
0
-20
20
log
⎛
⎝
RR-----21--_⎠⎞
MODULATOR
-40
GAIN
F_LC F_ESR
LOOP GAIN
-60
10
100
1k
10k 100k 1M 10M
FREQUENCY (Hz)
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Component Selection Guidelines
Charge Pump Capacitor Selection
A capacitor across pins CT1 and CT2 is required to create
the proper bias voltage for the ISL6406 when operating the
IC from 3.3V. Selecting the proper capacitance value is
important so that the bias current draw and the current
required by the MOSFET gates do not overburden the
capacitor. A conservative approach is presented in
Equation 6.
C_PUMP
=
I--_{B----I--A----S-----+-----I--G-----A---T----E-- ( 1.5 )}
V_CC(f_S)
(EQ. 6)
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern digital ICs can produce high transient load slew
rates. High-frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (Effective Series Resistance) and voltage rating
requirements rather than actual capacitance requirements.
High-frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. Use only specialized
low-ESR capacitors intended for switching-regulator
applications for the bulk capacitors. The bulk capacitor’s
ESR will determine the output ripple voltage and the initial
voltage drop after a high slew-rate transient. An aluminum
electrolytic capacitor’s ESR value is related to the case size
with lower ESR available in larger case sizes. However, the
Equivalent Series Inductance (ESL) of these capacitors
increases with case size and can reduce the usefulness of
the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case
size perform better than a single large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by Equations 7 and 8:
ΔI =
V_IN - V_OUT V_OUT
x
f_s x L
V_IN
(EQ. 7)
12
FN9073.7
January 16, 2007