ISL6263A Datasheet, PDF (14/19 Pages) Intersil Corporation – 5-Bit VID Single-Phase Voltage Regulator with Power Monitor for IMVP-6+ Santa Rosa GPU Core

ISL6263A
the drive voltage at the end of a PWM cycle is 200mV. One
will find that a bootstrap capacitance of at least 0.125µF is
required. The next larger standard value capacitance is
0.15µF. A good quality ceramic capacitor is recommended.
Soft-Start and Soft Dynamic VID Slew Rates
The output voltage of the converter tracks V_SOFT, the
voltage across the SOFT and VSS pins. Shown in Figure 1,
the SOFT pin is connected to the output of the VID DAC
through the unidirectional soft-start current source I_SS or the
bidirectional soft-dynamic VID current source I_DVID, and the
non-inverting input of the error amplifier. Current is sourced
from the SOFT pin when I_SS is active. The SOFT pin can
both source and sink current when I_DVID is active. The
soft-start capacitor C_SOFT changes voltage at a rate
proportional to I_SS or I_DVID. The ISL6263A automatically
selects I_SS for the soft-start sequence so that the inrush
current through the output capacitors is maintained below
the OCP threshold. Once soft-start has completed, I_DVID is
automatically selected for output voltage changes
commanded by the VID inputs, charging C_SOFT when the
output voltage is commanded to rise, and discharging
C_SOFT when the output voltage is commanded to fall.
The IMVP-6+ Render Voltage Regulator specification
requires a minimum of 10mV/µs for SLEWRATE_GFX. The
value for C_SOFT must guarantee the minimum slew-rate of
10mV/µs when the soft-dynamic VID current source I_DVID is
the minimum specified value in the “Electrical Specifications”
table on page 8. The value of C_SOFT, can be calculated from
Equation 4:
C_SOFT
=
-^I-^D-----^V----^I-^D-----^m----ⁱ--ⁿ- =
⎛
⎝
-¹---⁰-_μ---^m-_s----^V-- _⎠⎞
-¹---⁸---⁰----^μ----^A--
10 k
=
0.018 μ F
(EQ. 4)
Choosing the next lower standard component value of
0.015µF will guarantee 10mV/µs SLEWRATE_GFX. This
choice of C_SOFT controls the startup slew-rate as well. One
should expect the output voltage during soft-start to slew to
the voltage commanded by the VID settings at a nominal
rate given by Equation 5:
d_----V_{-----S---O-----F----T-}
dt
=
------^I--^S----^S-------
C_SOFT
=
-₀---_.-⁴⁰---²-₁---^μ₅----^A_μ----_F--≈ ²----^.--⁸-_μ--^m-_s-----^V--
(EQ. 5)
Note that the slewrate is the average rate of change
between the initial and final voltage values.
RBIAS Current Reference
The RBIAS pin is internally connected to a 1.545V reference
through a 3kΩ resistance. A bias current is established by
connecting a ±1% tolerance, 150kΩ resistor between the
RBIAS and VSS pins. This bias current is mirrored, creating the
reference current I_OCSET that is sourced from the OCSET pin.
Do not connect any other components to this pin, as they will
have a negative impact on the performance of the IC.
Setting the PWM Switching Frequency
The R³ modulator scheme is not a fixed-frequency
architecture, lacking a fixed-frequency clock signal to
produce PWM. The switching frequency increases during
the application of a load to improve transient performance.
The static PWM frequency varies slightly depending on the
input voltage, output voltage, and output current, but this
variation is normally less than 10% in continuous conduction
mode.
Refer to Figure 2 and find that resistor R_FSET is connected
between the V W and COMP pins. A current is sourced from
VW through R_FSET creating the synthetic ripple window
voltage signal V_W which determines the PWM switching
frequency. The relationship between the resistance of R_FSET
and the switching frequency in CCM is approximated by
Equation 6:
R_FSET
=
(_---T_{-----–-----}0_---._--5_----×_-----1_----0_---^–_---⁶_----)
400 × 10^–12
(EQ. 6)
For example, the value of R_FSET for 300kHz operation is
approximately:
7.1 ×10³
=
(_---3_---._--3_---3_-----×_-----1_---0_----^–_---⁶_{----–-----}0_---._--5_----×_-----1_----0_---^–_---⁶_----)
400 × 10^–12
(EQ. 7)
This relationship only applies to operation in constant
conduction mode because the PWM frequency naturally
decreases as the load decreases while in diode emulation
mode.
Static Droop Design Using DCR Sensing
The ISL6263A has an internal differential amplifier to
accurately regulate the voltage at the processor die.
For DCR sensing, the process to compensate the DCR
resistance variation takes several iterative steps. Figure 2
shows the DCR sensing method. Figure 8 shows the
simplified model of the droop circuitry. The inductor DC
current generates a DC voltage drop on the inductor DCR.
Equation 8 gives this relationship:
V_DCR = I_o ⋅ DCR
(EQ. 8)
An R-C network senses the voltage across the inductor to
get the inductor current information. R_NTCEQ represents the
NTC network consisting of R_NTC, R_{NTCS, and} R_NTCP. The
choice of R_S will be discussed in the following section.
The first step in droop load line compensation is to adjust
R_NTCEQ, and R_S such that the correct droop voltage
appears even at light loads between the VSUM and VO pins.
As a rule of thumb, the voltage drop V_N across the R_NTCEQ
network, is set to be 0.3x to 0.8x V_DCR. This gain, defined as
G₁, provides a reasonable amount of light load signal from
which to derive the droop voltage.
14
FN9284.3
July 8, 2010