ISL6263A Datasheet, PDF (13/19 Pages) Intersil Corporation – 5-Bit VID Single-Phase Voltage Regulator with Power Monitor for IMVP-6+ Santa Rosa GPU Core

ISL6263A
TABLE 3. FAULT PROTECTION SUMMARY OF ISL6263A
FAULT TYPE
FAULT
DURATION
PRIOR TO
PROTECTION
PROTECTION
ACTIONS
FAULT
RESET
Overcurrent
120µs
LGATE, UGATE, and Cycle
PGOOD latched low VR_ON or
VDD
Short Circuit
<2µs
LGATE, UGATE, and Cycle
PGOOD latched low VR_ON or
VDD
Overvoltage
(+195mV)
between VO pin
and SOFT pin
1ms
LGATE, UGATE, and Cycle
PGOOD latched low VR_ON or
VDD
Severe
Overvoltage
(+1.55V)
between VO pin
and VSS pin
Immediately
UGATE, and
Cycle
PGOOD latched low, VDD only
LGATE toggles ON
when VO >1.55V
OFF when
VO <0.77V
until fault reset
Undervoltage
(-300mV)
between VO pin
and SOFT pin
1ms
LGATE, UGATE, and Cycle
PGOOD latched low VR_ON or
VDD
PWM
LGATE
1V
UGATE
1V
t _PDRU
t _PDRL
FIGURE 6. GATE DRIVER TIMING DIAGRAM
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
Q_GATE = 100nC
0.4
0.2 _20nC
0.00.0 _{0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0}
ΔV_{BOOT_CAP} (V)
FIGURE 7. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
A severe overvoltage protection fault occurs immediately
after the voltage between the VO and VSS pins exceed the
rising severe-overvoltage threshold V_OVPS, which is 1.545V,
the same reference voltage used by the VID DAC. The
ISL6263A will latch UGATE and PGOOD low but unlike other
protective faults, LGATE remains high until the voltage
between VO and VSS falls below approximately 0.77V, at
which time LGATE is pulled low. The LGATE pin will continue
to switch high and low at 1.545V and 0.77V until VDD has
gone below the falling POR threshold voltage ^V_{VDD_THF.}
This provides maximum protection against a shorted
high-side MOSFET while preventing the output voltage from
ringing below ground. The severe-overvoltage fault circuit
can be triggered after another fault has already been
latched.
Gate-Driver Outputs LGATE and UGATE
The ISL6263A has internal high-side and low-side
N-Channel MOSFET gate-drivers. The LGATE driver is
optimized for low duty-cycle applications where the low-side
MOSFET conduction losses are dominant. The LGATE
pull-down resistance is very low in order to clamp the
gate-source voltage of the MOSFET below the V_GS(th) at
turnoff. The current transient through the low-side gate at
turnoff can be considerable due to the characteristic large
switching charge of a low r_DS(ON) MOSFET.
Adaptive shoot-through protection prevents the gate-driver
outputs from going high until the opposite gate-driver output
has fallen below approximately 1V. The UGATE turn-on
propagation delay t_PDRU and LGATE turn-on propagation
delay t_PDRL are found in the “Electrical Specifications” table
on page 7. The power for the LGATE gate-driver is sourced
directly from the PVCC pin. The power for the UGATE
gate-driver is sourced from a boot-strap capacitor connected
across the BOOT and PHASE pins. The boot capacitor is
charged from PVCC through an internal boot-strap diode
each time the low-side MOSFET turns on, pulling the
PHASE pin low.
Internal Bootstrap Diode
The ISL6263A has an integrated boot-strap Schottky diode
connected from the PVCC pin to the BOOT pin. Simply
adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circuit.
The minimum value of the bootstrap capacitor can be
calculated from Equation 3:
C_B
O
OT
≥
---^Q----^G-----^A----^T---^E----
ΔV_BOOT
(EQ. 3)
where Q_GATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The ΔV_BOOT term is
defined as the allowable droop in the rail of the upper drive.
As an example, suppose an upper MOSFET has a gate
charge, Q_GATE, of 25nC at 5V and also assume the droop in
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FN9284.3
July 8, 2010