KU386 Datasheet, PDF (80/102 Pages) Intel Corporation – SX MICROPROCESSOR

Intel386^TM SX MICROPROCESSOR
5 The Intel386 DX CPU uses A₃₁ and M IO as
selects for the numerics coprocessor The
Intel386 SX CPU uses A₂₃ and M IO as selects
6 The Intel386 DX CPU prefetch unit fetches code
in four-byte units The Intel386 SX CPU prefetch
unit reads two bytes as one unit (like the 80286)
In BS16 mode the Intel386 DX CPU takes two
consecutive bus cycles to complete a prefetch re-
quest If there is a data read or write request after
the prefetch starts the Intel386 DX CPU will fetch
all four bytes before addressing the new request
7 Both Intel386 DX CPU and Intel386 SX CPU have
the same logical address space The only differ-
ence is that the Intel386 DX CPU has a 32-bit
physical address space and the Intel386 SX CPU
has a 24-bit physical address space The Intel386
SX CPU has a physical memory address space of
up to 16 megabytes instead of the 4 gigabytes
available to the Intel386 DX CPU Therefore in
Intel386 SX CPU systems the operating system
must be aware of this physical memory limit and
should allocate memory for applications programs
within this limit If a Intel386 DX CPU system uses
only the lower 16 megabytes of physical address
then there will be no extra effort required to mi-
grate Intel386 DX CPU software to the Intel386
SX CPU Any application which uses more than
16 megabytes of memory can run on the Intel386
SX CPU if the operating system utilizes the
Intel386 SX CPU’s paging mechanism In spite of
this difference in physical address space the
Intel386 SX CPU and Intel386 DX CPU can run
the same operating systems and applications
within their respective physical memory con-
straints
8 The Intel386 SX has an input called FLT which
tri-states all bidirectional and output pins includ-
ing HLDA when asserted It is used with ON
Circuit Emulation (ONCE) In the Intel386 DX
CPU FLT is found only on the plastic quad flat
package version and not on the ceramic pin grid
array version For a more detailed explanation of
FLT and testability please refer to section 5 4
9 0 INSTRUCTION SET
This section describes the instruction set Table 9 1
lists all instructions along with instruction encoding
diagrams and clock counts Further details of the
instruction encoding are then provided in the follow-
ing sections which completely describe the encod-
ing structure and the definition of all fields occurring
within instructions
9 1 Intel386^TM SX CPU Instruction
Encoding and Clock Count
Summary
To calculate elapsed time for an instruction multiply
the instruction clock count as listed in Table 9 1 be-
80
low by the processor clock period (e g 62 5 ns
for an Intel386 SX Microprocessor operating at
16 MHz) The actual clock count of an Intel386 SX
Microprocessor program will average 5% more than
the calculated clock count due to instruction se-
quences which execute faster than they can be
fetched from memory
Instruction Clock Count Assumptions
1 The instruction has been prefetched decoded
and is ready for execution
2 Bus cycles do not require wait states
3 There are no local bus HOLD requests delaying
processor access to the bus
4 No exceptions are detected during instruction ex-
ecution
5 If an effective address is calculated it does not
use two general register components One regis-
ter scaling and displacement can be used within
the clock counts shown However if the effective
address calculation uses two general register
components add 1 clock to the clock count
shown
Instruction Clock Count Notation
1 If two clock counts are given the smaller refers to
a register operand and the larger refers to a mem-
ory operand
2 n ^e number of times repeated
3 m ^e number of components in the next instruc-
tion executed where the entire displacement (if
any) counts as one component the entire imme-
diate data (if any) counts as one component and
all other bytes of the instruction and prefix(es)
each count as one component
Misaligned or 32-Bit Operand Accesses
If instructions accesses a misaligned 16-bit oper-
and or 32-bit operand on even address add
2 clocks for read or write
4 clocks for read and write
If instructions accesses a 32-bit operand on odd
address add
4 clocks for read or write
8 clocks for read and write
Wait States
Wait states add 1 clock per wait state to instruction
execution for each data access