KU386 Datasheet, PDF (51/102 Pages) Intel Corporation – SX MICROPROCESSOR

Intel386^TM SX MICROPROCESSOR
Bus cycles always begin with T1 T1 always leads to
T2 If a bus cycle is not acknowledged during T2 and
NA is inactive T2 is repeated When a cycle is
acknowledged during T2 the following state will be
T1 of the next bus cycle if a bus request is pending
internally or T_i if there is no bus request pending or
T_h if the HOLD input is being asserted
Use of pipelined address allows the Intel386 SX Mi-
croprocessor to enter three additional bus states not
shown in Figure 5 8 Figure 5 12 is the complete bus
state diagram including pipelined address cycles
Pipelined Address
Address pipelining is the option of requesting the
address and the bus cycle definition of the next in-
ternally pending bus cycle before the current bus
cycle is acknowledged with READY asserted
ADS is asserted by the Intel386 SX Microproces-
sor when the next address is issued The address
pipelining option is controlled on a cycle-by-cycle
basis with the NA input signal
Once a bus cycle is in progress and the current ad-
dress has been valid for at least one entire bus
state the NA input is sampled at the end of every
phase one until the bus cycle is acknowledged Dur-
ing non-pipelined bus cycles NA is sampled at the
end of phase one in every T2 An example is Cycle 2
in Figure 5 9 during which NA is sampled at the
end of phase one of every T2 (it was asserted once
during the first T2 and has no further effect during
that bus cycle)
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Following any idle bus state (Ti) addresses are non-pipelined Within non-pipelined bus cycles NA is only sampled
during wait states Therefore to begin address pipelining during a group of non-pipelined bus cycles requires a non-pipe-
lined cycle with at least one wait state (Cycle 2 above)
Figure 5 9 Transitioning to Pipelined Address During Burst of Bus Cycles
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