KU386 Datasheet, PDF (21/102 Pages) Intel Corporation – SX MICROPROCESSOR

Intel386^TM SX MICROPROCESSOR
TLB TESTING
The Intel386 SX Microprocessor also provides a
mechanism for testing the Translation Lookaside
Buffer (TLB) if desired This particular mechanism
may not be continued in the same way in future
processors
There are two TLB testing operations 1) writing en-
tries into the TLB and 2) performing TLB lookups
Two Test Registers shown in Figure 2 6 are provid-
ed for the purpose of testing TR6 is the ‘‘test com-
mand register’’ and TR7 is the ‘‘test data register’’
For a more detailed explanation of testing the TLB
see the Intel386^TM SX Microprocessor Program-
mer’s Reference Manual
2 10 Debugging Support
The Intel386 SX Microprocessor provides several
features which simplify the debugging process The
three categories of on-chip debugging aids are
1 The code execution breakpoint opcode (0CCH)
2 The single-step capability provided by the TF bit
in the flag register
3 The code and data breakpoint capability provided
by the Debug Registers DR0–3 DR6 and DR7
BREAKPOINT INSTRUCTION
A single-byte software interrupt (Int 3) breakpoint in-
struction is available for use by software debuggers
The breakpoint opcode is 0CCh and generates an
exception 3 trap when executed
SINGLE-STEP TRAP
If the single-step flag (TF bit 8) in the EFLAG regis-
ter is found to be set at the end of an instruction a
single-step exception occurs The single-step ex-
ception is auto vectored to exception number 1
DEBUG REGISTERS
The Debug Registers are an advanced debugging
feature of the Intel386 SX Microprocessor They al-
low data access breakpoints as well as code execu-
tion breakpoints Since the breakpoints are indicated
by on-chip registers an instruction execution break-
point can be placed in ROM code or in code shared
by several tasks neither of which can be supported
by the INT 3 breakpoint opcode
The Intel386 SX Microprocessor contains six Debug
Registers consisting of four breakpoint address reg-
isters and two breakpoint control registers Initially
after reset breakpoints are in the disabled state
therefore no breakpoints will occur unless the de-
bug registers are programmed Breakpoints set up in
the Debug Registers are auto-vectored to exception
1 Figure 2 7 shows the breakpoint status and con-
trol registers
Figure 2 6 Test Registers
240187 – 7
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