KU386 Datasheet, PDF (4/102 Pages) Intel Corporation – SX MICROPROCESSOR

Intel386^TM SX MICROPROCESSOR
1 0 PIN DESCRIPTION (Continued)
The following are the Intel386^TM SX Microprocessor pin descriptions The following definitions are used in the
pin descriptions
The named signal is active LOW
I
Input signal
O Output signal
I O Input and Output signal
-
No electrical connection
Symbol
CLK2
RESET
D₁₅ – D₀
A₂₃ – A₁
WR
DC
M IO
LOCK
ADS
NA
READY
BHE BLE
Type
Pin
I 15
I 33
I O 81-83 86-90
92-96 99-100 1
O 80-79 76-72 70
66-64 62-58
56-51 18
O 25
O 24
O 23
O 26
O 16
I6
I7
O 19 17
Name and Function
CLK2 provides the fundamental timing for the Intel386 SX
Microprocessor For additional information see Clock
RESET suspends any operation in progress and places the
Intel386 SX Microprocessor in a known reset state See
Interrupt Signals for additional information
Data Bus inputs data during memory I O and interrupt
acknowledge read cycles and outputs data during memory and
I O write cycles See Data Bus for additional information
Address Bus outputs physical memory or port I O addresses
See Address Bus for additional information
Write Read is a bus cycle definition pin that distinguishes write
cycles from read cycles See Bus Cycle Definition Signals for
additional information
Data Control is a bus cycle definition pin that distinguishes data
cycles either memory or I O from control cycles which are
interrupt acknowledge halt and code fetch See Bus Cycle
Definition Signals for additional information
Memory IO is a bus cycle definition pin that distinguishes
memory cycles from input output cycles See Bus Cycle
Definition Signals for additional information
Bus Lock is a bus cycle definition pin that indicates that other
system bus masters are not to gain control of the system bus
while it is active See Bus Cycle Definition Signals for
additional information
Address Status indicates that a valid bus cycle definition and
address (W R D C M IO BHE BLE and A₂₃ – A₁ are
being driven at the Intel386 SX Microprocessor pins See Bus
Control Signals for additional information
Next Address is used to request address pipelining See Bus
Control Signals for additional information
Bus Ready terminates the bus cycle See Bus Control Signals
for additional information
Byte Enables indicate which data bytes of the data bus take part
in a bus cycle See Address Bus for additional information
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