KU386 Datasheet, PDF (41/102 Pages) Intel Corporation – SX MICROPROCESSOR

Intel386^TM SX MICROPROCESSOR
ADDRESS BUS (A₂₃ – A₁ BHE BLE )
These three-state outputs provide physical memory
addresses or I O port addresses A₂₃ – A₁₆ are LOW
during I O transfers except for I O transfers auto-
matically generated by coprocessor instructions
During coprocessor I O transfers A₂₂ – A₁₆ are driv-
en LOW and A₂₃ is driven HIGH so that this ad-
dress line can be used by external logic to generate
the coprocessor select signal Thus the I O address
driven by the Intel386 SX Microprocessor for co-
processor commands is 8000F8H the I O address-
es driven by the Intel386 SX Microprocessor for co-
processor data are 8000FCH or 8000FEH for cycles
to the Intel387^TM SX
write and read cycles D C distinguishes between
data and control cycles M IO distinguishes be-
tween memory and I O cycles and LOCK distin-
guishes between locked and unlocked bus cycles
All of these signals are active LOW and will float
during bus acknowledge
The primary bus cycle definition signals are W R
D C and M IO since these are the signals driv-
en valid as ADS (Address Status output) becomes
active The LOCK is driven valid at the same time
the bus cycle begins which due to address pipelin-
ing could be after ADS becomes active Exact bus
cycle definitions as a function of W R D C and
M IO are given in Table 5 2
The address bus is capable of addressing 16 mega-
bytes of physical memory space (000000H through
FFFFFFH) and 64 kilobytes of I O address space
(000000H through 00FFFFH) for programmed I O
The address bus is active HIGH and will float during
bus hold acknowledge
The Byte Enable outputs BHE and BLE directly
indicate which bytes of the 16-bit data bus are in-
volved with the current transfer BHE applies to
D₁₅ – D₈ and BLE applies to D₇ – D₀ If both BHE
and BLE are asserted then 16 bits of data are
being transferred See Table 5 1 for a complete de-
coding of these signals The byte enables are active
LOW and will float during bus hold acknowledge
BUS CYCLE DEFINITION SIGNALS
(W R D C M IO LOCK )
These three-state outputs define the type of bus cy-
cle being performed W R distinguishes between
LOCK indicates that other system bus masters are
not to gain control of the system bus while it is ac-
tive LOCK is activated on the CLK2 edge that be-
gins the first locked bus cycle (i e it is not active at
the same time as the other bus cycle definition pins)
and is deactivated when ready is returned at the end
of the last bus cycle which is to be locked The be-
ginning of a bus cycle is determined when READY
is returned in a previous bus cycle and another is
pending (ADS is active) or by the clock edge in
which ADS is driven active if the bus was idle This
means that it follows more closely with the write
data rules when it is valid but may cause the bus to
be locked longer than desired The LOCK signal
may be explicitly activated by the LOCK prefix on
certain instructions LOCK is always asserted
when executing the XCHG instruction during de-
scriptor updates and during the interrupt acknowl-
edge sequence
Table 5 1 Byte Enable Definitions
BHE
BLE
Function
0
0
Word Transfer
0
1
Byte transfer on upper byte of the data bus D₁₅ – D₈
1
0
Byte transfer on lower byte of the data bus D₇ – D₀
1
1
Never occurs
Table 5 2 Bus Cycle Definition
M IO
DC
WR
Bus Cycle Type
Locked
0
0
0
Interrupt Acknowledge
Yes
0
0
1
does not occur
0
1
0
I O Data Read
No
0
1
1
I O Data Write
No
1
0
0
Memory Code Read
No
1
0
1
Halt
Shutdown
No
Address ^e 2 Address ^e 0
BHE ^e 1 BHE ^e 1
BLE ^e 0 BLE ^e 0
1
1
0
Memory Data Read
Some Cycles
1
1
1
Memory Data Write
Some Cycles
41