82562G Datasheet, PDF (8/44 Pages) Intel Corporation – Mbps Platform LAN Connect

82562G — Networking Silicon
I_I/_/O_O C_Coo_nn_tt_rr_oo_l l_HH_ubub₄
LA(NICCH4o)nLtrAoNller
Controller
82562EZ
8^(P2^l5^a6^tf2^orG^m P^LAL^NC
Connect
Device)
Transmit Differential Pair
(TDP/TDN)
Receive Differential Pair
(RDP/RDN)
System Bus Interface
Magnetics
Figure 2. 82562G PLC 10/100 Mbps Ethernet Solution
2.1.1
Reset/Synchronize Operations
The Reset/Synchronize signal used by the LAN Connect Interface is driven by the ICHx integrated
LAN device. It has two functions:
• Synchronize. When this pin is activated synchronously for only one LAN connect clock, it is
used for synchronization between the ICHx integrated LAN and PHY on LAN connect word
boundaries.
• Reset. When this pin is asserted beyond one LAN connect clock, the 82562G uses this signal
as a reset signal. To ensure a reset of the 82562G, the reset should remain active for at least
500 µs.
2.1.2
Reset Considerations
When the 82562G Reset signal (JRSTSYNC) is asserted for at least 500 µs, all internal circuits are
reset. The 82562G can also be reset by setting the MII register Reset bit equal to 1 (Register 0, bit
15).
The 82562G filters out JRSTSYNC pulses with a width of less than 200 ns to distinguish between
a reset and synchronize pulse. Again, the Reset signal should be longer than 500 µs to reset the
82562G.
4
Datasheet