82562G Datasheet, PDF (13/44 Pages) Intel Corporation – Mbps Platform LAN Connect

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Networking Silicon — 82562G
82562G Signal Descriptions
Signal Type Definitions
Type
I
O
I/O
MLT
B
DPS
APS
Name
Description
Input
Input pin to the 82562G.
Output
Output pin from the 82562G.
Input/Output Multiplexed input and output pin to and from the 82562G.
Multi-level
analog I/O
Multi-level analog pin used for input and output.
Bias
Bias pin used for ground connection through a resistor or an external voltage
reference.
Digital Power Digital power or ground pin for the 82562G.
Supply
Analog Power Analog power or ground pin for the 82562G.
Supply
Twisted Pair Ethernet (TPE) Pins
Pin Name
TDP
TDN
RDP
RDN
Pin
Number
Type
10
MLT
11
15
MLT
16
Description
Transmit Differential Pair. The transmit differential pair sends serial bit
streams to the unshielded twisted pair (UTP) cable. The differential pair is
a two-level signal in 10BASE-T (Manchester) mode and a three-level
signal in 100BASE-TX mode (MLT-3). These signals directly interface
with the isolation transformer.
Receive Differential Pair. The receive differential pair receive the serial
bit stream from an unshielded twisted pair (UTP) cable. The differential
pair is a two-level signal in 10BASE-T mode (Manchester) or a three-level
signal in 100BASE-TX mode (MLT-3). These signals directly interface
with an isolation transformer.
External Bias Pins
Pin Name
Pin
Number
Type
Description
RBIAS10
4
RBIAS100 5
B
Reference Bias Resistor (100 Mbps). This pin should be connected to a
pull-down resistor.^a
B
Reference Bias Resistor (10 Mbps). This pin should be connected to a
pull-down resistor.^a
a. Based on some board designs, RBIAS100 and RBIAS10 values may need to be increased/decreased to compensate for high/
low MDI transmit amplitude. See the 82562G/GT and 82562ET/EM LAN on Motherboard Design Guide for more information.
Datasheet
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