82562G Datasheet, PDF (7/44 Pages) Intel Corporation – Mbps Platform LAN Connect

Networking Silicon — 82562G
2.0
82562G Architectural Overview
The 82562G PLC is a 3.3 V device in a 48-pin Shrink Small Outline Package (SSOP) that is
designed to work only in Data Terminal Equipment (DTE) mode. In normal operating mode, the
82562G incorporates all active circuitry required to interface with the Intel^® ICHx device with an
integrated 10/100 Mbps LAN controller. The 82562G supports a direct interface to all Media
Access Control (MAC) components that meet the Platform LAN connect interface specification.
Figure 1 shows a block diagram of the 82562G architecture.
RDN/RDP
TDN/TDP
Digital
Equalizer
Adaptation
Equalizer &
BLW correction
Digital Clock
Recovery (100)
CRS/Link 10
Detection
Digital Clock
Recovery (10)
Transmit DAC
10/100
Bias & Band-
Gap Voltage
Circuit
Clock
Generator
100Base-TX
PCS
10Base-T
PCS
Auto-
Negotiation
Control
Registers
Port LED
Drivers
LILED#
ACTLED#
SPDLED#
LAN
Connect
Interface
JRSTSYNC
JTXD[2:0]
3
3
JRXD[2:0]
JCLK
X1
Crystal
X2
25 MHz
Figure 1. 82562G PLC Block Diagram
2.1
LAN Connect Interface
The 82562G supports a LAN Connect Interface (LCI) as specified in the LCI Specification. The
LAN Connect is the I/O Control Hub 2 (ICH2) interface to the 82562G. The LCI uses an 8-pin
interface, which reduces the pin count from 15, for an Media Independent Interface (MII) PHY. In
addition, its signaling protocol provides greater functionality, such as dynamic power reduction,
from a PLC in comparison to a standard MII PHY.
Figure 2 shows how the 82562G can be used in a 10/100 Mbps ICHx design.
Datasheet
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