82562G Datasheet, PDF (28/44 Pages) Intel Corporation – Mbps Platform LAN Connect

82562G — Networking Silicon
6.3.2
6.3.3
Register 17: PHY Unit Special Control Bit Definitions
Bit(s)
Name
Description
15
Scrambler By-
0 = Normal operations
pass
1 = By-pass scrambler
14
By-pass 4B/5B 0 = Normal operation
1 = 4 bit to 5 bit by-pass
13
Force Transmit H- 0 = Normal operation
Pattern
1 = Force transmit H-pattern
12
Force 34
0 = Normal operation
Transmit Pattern _{1 = Force 34 transmit pattern}
11
Valid Link
0 = Normal operation
1 = 100BASE-TX valid link
10
Symbol Error
0 = Normal operation
Enable
1 = Symbol error output is enabled
9
Carrier Sense
This bit controls the receive 100 carrier sense disable
Disable
function.
0 = Carrier sense enabled
1 = Carrier sense disabled
8
Disable Dynamic 0 = Dynamic Power-Down enabled
Power-Down
1 = Dynamic Power-Down disabled
7
Auto-Negotiation 0 = Auto-Negotiation normal mode
Loopback
1 = Auto-Negotiation loopback
6
MDI Tri-State
0 = Normal operation
1 = MDI Tri-state (transmit driver tri-states)
5
Force Polarity
0 = Normal polarity
1 = Reversed polarity
4
Auto Polarity
0 = Normal polarity operation
Disable
1 = Auto Polarity disabled
3
Squelch Disable 0 = Normal squelch operation
1 = 10BASE-T squelch test disable
2
Extended
Squelch
1 = 10BASE-T Extended Squelch control enabled
0 = 10BASE-T Extended Squelch control disabled
1
Link Integrity
0 = Normal Link Integrity operation
Disable
1 = Link disabled
0
Jabber Function 0 = Normal Jabber operation
Disable
1 = Jabber disabled
Default
0
R/W
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
Register 18: Reserved
Bit(s)
Name
15:0 Reserved
Description
These bits are reserved and should be set to a
constant 0.
Default
0
R/W
RO
24
Datasheet