82562G Datasheet, PDF (27/44 Pages) Intel Corporation – Mbps Platform LAN Connect

Networking Silicon — 82562G
6.2
6.3
6.3.1
MDI Registers 8 through 15
Registers 8 through 15 are reserved for IEEE.
MDI Registers 16 through 31
Register 16: PHY Status and Control Register Bit Definitions
Bit(s)
Name
Description
15:14
13
12
11
10
9
8
7
6:2
1
0
Reserved
These bits are reserved and should be set to 00b.
Reduced Power
Down Disable
This bit disables the automatic reduced power down.
0 = Enable automatic reduced power down
1 = Disable automatic reduced power down
Reserved
This bit is reserved and should be set to 0b.
Receive De-
This bit indicates status of the 100BASE-TX Receive
Serializer In-Sync De-Serializer In-Sync.
Indication
100BASE-TX
Power-Down
This bit indicates the power state of 100BASE-TX
PHY unit.
0 = Normal operation
1 = Power-down
10BASE-T
Power-Down
This bit indicates the power state of 10BASE-T PHY
unit.
0 = Normal operation
1 = Power-Down
Polarity
This bit indicates 10BASE-T polarity.
0 = Normal polarity
1 = Reverse polarity
Reserved
This bit is reserved and should be set to 0b.
PHY Address
These bits contain the sampled PHY address.
Speed
This bit indicates the Auto-Negotiation result.
0 = 10 Mbps
1 = 100 Mbps
Duplex Mode
This bit indicates the Auto-Negotiation result.
0 = Half-duplex
1 = Full-duplex
Default
00
1
R/W
RW
RW
0
RW
--
RO
1
RO
1
RO
--
RO
0
RO
--
RO
--
RO
--
RO
Datasheet
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