82C54 Datasheet, PDF (6/18 Pages) Intel Corporation – CHMOS PROGRAMMABLE INTERVAL TIMER

82C54
Write Operations
The programming procedure for the 82C54 is very
flexible Only two conventions need to be remem-
bered
1) For each Counter the Control Word must be
written before the initial count is written
2) The initial count must follow the count format
specified in the Control Word (least significant
byte only most significant byte only or least sig-
nificant byte and then most significant byte)
Since the Control Word Register and the three
Counters have separate addresses (selected by the
A₁ A₀ inputs) and each Control Word specifies the
Counter it applies to (SC0 SC1 bits) no special in-
struction sequence is required Any programming
sequence that follows the conventions above is ac-
ceptable
A new initial count may be written to a Counter at
any time without affecting the Counter’s pro-
grammed Mode in any way Counting will be affected
as described in the Mode definitions The new count
must follow the programmed count format
If a Counter is programmed to read write two-byte
counts the following precaution applies A program
must not transfer control between writing the first
and second byte to another routine which also writes
into that same Counter Otherwise the Counter will
be loaded with an incorrect count
A₁ A₀
Control Word Counter 0 1
1
LSB of count Counter 0 0
0
MSB of count Counter 0 0
0
Control Word Counter 1 1
1
LSB of count Counter 1 0
1
MSB of count Counter 1 0
1
Control Word Counter 2 1
1
LSB of count Counter 2 1
0
MSB of count Counter 2 1
0
A₁ A₀
Control Word Counter 2 1
1
Control Word Counter 1 1
1
Control Word Counter 0 1
1
LSB of count Counter 2 1
0
MSB of count Counter 2 1
0
LSB of count Counter 1 0
1
MSB of count Counter 1 0
1
LSB of count Counter 0 0
0
MSB of count Counter 0 0
0
A₁ A₀
Control Word Counter 0 1
1
Counter Word Counter 1 1
1
Control Word Counter 2 1
1
LSB of count Counter 2 1
0
LSB of count Counter 1 0
1
LSB of count Counter 0 0
0
MSB of count Counter 0 0
0
MSB of count Counter 1 0
1
MSB of count Counter 2 1
0
A₁ A₀
Control Word Counter 1 1
1
Control Word Counter 0 1
1
LSB of count Counter 1 0
1
Control Word Counter 2 1
1
LSB of count Counter 0 0
0
MSB of count Counter 1 0
1
LSB of count Counter 2 1
0
MSB of count Counter 0 0
0
MSB of count Counter 2 1
0
NOTE
In all four examples all counters are programmed to read write two-byte counts
These are only four of many possible programming sequences
Figure 8 A Few Possible Programming Sequences
Read Operations
It is often desirable to read the value of a Counter
without disturbing the count in progress This is easi-
ly done in the 82C54
There are three possible methods for reading the
counters a simple read operation the Counter
Latch Command and the Read-Back Command
Each is explained below The first method is to per-
form a simple read operation To read the Counter
which is selected with the A1 A0 inputs the CLK
input of the selected Counter must be inhibited by
using either the GATE input or external logic Other-
wise the count may be in the process of changing
when it is read giving an undefined result
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