82C54 Datasheet, PDF (11/18 Pages) Intel Corporation – CHMOS PROGRAMMABLE INTERVAL TIMER

82C54
MODE 2 RATE GENERATOR
This Mode functions like a divide-by-N counter It is
typicially used to generate a Real Time Clock inter-
rupt OUT will initially be high When the initial count
has decremented to 1 OUT goes low for one CLK
pulse OUT then goes high again the Counter re-
loads the initial count and the process is repeated
Mode 2 is periodic the same sequence is repeated
indefinitely For an initial count of N the sequence
repeats every N CLK cycles
GATE ^e 1 enables counting GATE ^e 0 disables
counting If GATE goes low during an output pulse
OUT is set high immediately A trigger reloads the
Counter with the initial count on the next CLK pulse
OUT goes low N CLK pulses after the trigger Thus
the GATE input can be used to synchronize the
Counter
After writing a Control Word and initial count the
Counter will be loaded on the next CLK pulse OUT
goes low N CLK Pulses after the initial count is writ-
ten This allows the Counter to be synchronized by
software also
231244 – 10
NOTE
A GATE transition should not occur one clock prior to
terminal count
Figure 17 Mode 2
Writing a new count while counting does not affect
the current counting sequence If a trigger is re-
ceived after writing a new count but before the end
of the current period the Counter will be loaded with
the new count on the next CLK pulse and counting
will continue from the new count Otherwise the
new count will be loaded at the end of the current
counting cycle In mode 2 a COUNT of 1 is illegal
MODE 3 SQUARE WAVE MODE
Mode 3 is typically used for Baud rate generation
Mode 3 is similar to Mode 2 except for the duty cycle
of OUT OUT will initially be high When half the ini-
tial count has expired OUT goes low for the remain-
der of the count Mode 3 is periodic the sequence
above is repeated indefinitely An initial count of N
results in a square wave with a period of N CLK
cycles
GATE ^e 1 enables counting GATE ^e 0 disables
counting If GATE goes low while OUT is low OUT is
set high immediately no CLK pulse is required A
trigger reloads the Counter with the initial count on
the next CLK pulse Thus the GATE input can be
used to synchronize the Counter
After writing a Control Word and initial count the
Counter will be loaded on the next CLK pulse This
allows the Counter to be synchronized by software
also
Writing a new count while counting does not affect
the current counting sequence If a trigger is re-
ceived after writing a new count but before the end
of the current half-cycle of the square wave the
Counter will be loaded with the new count on the
next CLK pulse and counting will continue from the
new count Otherwise the new count will be loaded
at the end of the current half-cycle
Mode 3 is implemented as follows
Even counts OUT is initially high The initial count is
loaded on one CLK pulse and then is decremented
by two on succeeding CLK pulses When the count
expires OUT changes value and the Counter is re-
loaded with the initial count The above process is
repeated indefinitely
Odd counts OUT is initially high The initial count
minus one (an even number) is loaded on one CLK
pulse and then is decremented by two on succeed-
ing CLK pulses One CLK pulse after the count ex-
pires OUT goes low and the Counter is reloaded
with the initial count minus one Succeeding CLK
pulses decrement the count by two When the count
expires OUT goes high again and the Counter is
reloaded with the initial count minus one The above
process is repeated indefinitely So for odd counts
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