82C54 Datasheet, PDF (13/18 Pages) Intel Corporation – CHMOS PROGRAMMABLE INTERVAL TIMER

82C54
After writing the Control Word and initial count the
counter will not be loaded until the CLK pulse after a
trigger This CLK pulse does not decrement the
count so for an initial count of N OUT does not
strobe low until N^a1 CLK pulses after a trigger
A trigger results in the Counter being loaded with the
initial count on the next CLK pulse The counting
sequence is retriggerable OUT will not strobe low
for N ^a 1 CLK pulses after any trigger GATE has
no effect on OUT
If a new count is written during counting the current
counting sequence will not be affected If a trigger
occurs after the new count is written but before the
current count expires the Counter will be loaded
with the new count on the next CLK pulse and
counting will continue from there
Signal
Status
Modes
Low
Or Going
Low
Rising
High
0
Disables
counting
Enables
counting
1
1) Initiates
counting
2) Resets output
after next
clock
2
1) Disables
counting
2) Sets output
immediately
high
Initiates
counting
Enables
counting
3
1) Disables
counting
2) Sets output
immediately
high
Initiates
counting
Enables
counting
4
Disables
counting
Enables
counting
5
Initiates
counting
Figure 21 Gate Pin Operations Summary
MODE
MIN
COUNT
MAX
COUNT
0
1
0
1
1
0
2
2
0
3
2
0
4
1
0
NOTE
0 is equivalent to 2¹⁶ for binary counting and 10⁴ for
BCD counting
Figure 22 Minimum and Maximum initial Counts
Figure 20 Mode 5
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