82C54 Datasheet, PDF (12/18 Pages) Intel Corporation – CHMOS PROGRAMMABLE INTERVAL TIMER

82C54
OUT will be high for (N ^a 1) 2 counts and low for
(N ^b1) 2 counts
1) Writing the first byte has no effect on counting
2) Writing the second byte allows the new count to
be loaded on the next CLK pulse
This allows the sequence to be ‘‘retriggered’’ by
software OUT strobes low N^a1 CLK pulses after
the new count of N is written
231244 – 11
NOTE
A GATE transition should not occur one clock prior to
terminal count
Figure 18 Mode 3
MODE 4 SOFTWARE TRIGGERED STROBE
OUT will be initially high When the initial count ex-
pires OUT will go low for one CLK pulse and then
go high again The counting sequence is ‘‘triggered’’
by writing the initial count
GATE ^e 1 enables counting GATE ^e 0 disables
counting GATE has no effect on OUT
After writing a Control Word and initial count the
Counter will be loaded on the next CLK pulse This
CLK pulse does not decrement the count so for an
initial count of N OUT does not strobe low until
N ^a 1 CLK pulses after the initial count is written
If a new count is written during counting it will be
loaded on the next CLK pulse and counting will con-
tinue from the new count If a two-byte count is writ-
ten the following happens
Figure 19 Mode 4
231244 – 12
MODE 5 HARDWARE TRIGGERED STROBE
(RETRIGGERABLE)
OUT will initially be high Counting is triggered by a
rising edge of GATE When the initial count has ex-
pired OUT will go low for one CLK pulse and then
go high again
12