80C186XL Datasheet, PDF (34/48 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186XL 80C188XL
AC SPECIFICATIONS (Continued)
272431 – 12
NOTES
1 Status inactive in state preceding T₄
2 The data hold time lasts only until INTA goes inactive even if the INTA transition occurs prior to T_CLDX (min)
3 INTA occurs one clock later in Slave Mode
4 For write cycle followed by interrupt acknowledge cycle
5 LOCK is active upon T₁ of the first interrupt acknowledge cycle and inactive upon T₂ of the second interrupt acknowl-
edge cycle
6 Changes in T-state preceding next bus cycle if followed by write
Pin names in parentheses apply to the 80C188XL
Figure 8 Interrupt Acknowledge Cycle Waveforms
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