80C186XL Datasheet, PDF (12/48 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186XL 80C188XL
Table 3 Pin Descriptions (Continued)
Pin
Name
Pin Input Output
Type Type States
Pin Description
BHE
O
(RFSH)
H(Z)
R(Z)
The BHE (Bus High Enable) signal is analogous to A0 in that it is
used to enable data on to the most significant half of the data bus
pins D15 – D8 BHE will be LOW during T₁ when the upper byte is
transferred and will remain LOW through T₃ and T_W BHE does not
need to be latched On the 80C188XL RFSH is asserted LOW to
indicate a refresh bus cycle
In Enhanced Mode BHE (RFSH) will also be used to signify DRAM
refresh cycles A refresh cycle is indicated by both BHE (RFSH) and
A0 being HIGH
80C186XL BHE and A0 Encodings
BHE A0
Value Value
Function
0
0 Word Transfer
0
1 Byte Transfer on upper half of data bus
(D15 – D8)
1
0 Byte Transfer on lower half of data bus (D₇ – D₀)
1
1 Refresh
ALE QS0 O
H(0) Address Latch Enable Queue Status 0 is provided by the processor
R(0) to latch the address ALE is active HIGH with addresses guaranteed
valid on the trailing edge
WR QS1
O
H(Z)
R(Z)
Write Strobe Queue Status 1 indicates that the data on the bus is to
be written into a memory or an I O device It is active LOW When
the processor is in Queue Status Mode the ALE QS0 and WR QS1
pins provide information about processor instruction queue
interaction
QS1 QS0
Queue Operation
0
0 No queue operation
0
1 First opcode byte fetched from the queue
1
1 Subsequent byte fetched from the queue
1
0 Empty the queue
RD QSMD O
H(Z)
R(1)
Read Strobe is an active LOW signal which indicates that the
processor is performing a memory or I O read cycle It is guaranteed
not to go LOW before the A D bus is floated An internal pull-up
ensures that RD QSMD is HIGH during RESET Following RESET
the pin is sampled to determine whether the processor is to provide
ALE RD and WR or queue status information To enable Queue
Status Mode RD must be connected to GND
ARDY
I A(L)
S(L)
Asynchronous Ready informs the processor that the addressed
memory space or I O device will complete a data transfer The
ARDY pin accepts a rising edge that is asynchronous to CLKOUT
and is active HIGH The falling edge of ARDY must be synchronized
to the processor clock Connecting ARDY HIGH will always assert
the ready condition to the CPU If this line is unused it should be tied
LOW to yield control to the SRDY pin
NOTE
Pin names in parentheses apply to the 80C188XL
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