80C186XL Datasheet, PDF (11/48 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186XL 80C188XL
Pin
Name
TMR IN 0
TMR IN 1
TMR OUT 0
TMR OUT 1
DRQ0
DRQ1
NMI
INT0
INT1 SELECT
INT2 INTA0
INT3 INTA1 IRQ
A19 S6
A18 S5
A17 S4
A16 S3
(A8 – A15)
AD0 – AD15
(AD0 – AD7)
Pin
Type
I
O
I
I
I
IO
O
IO
Table 3 Pin Descriptions (Continued)
Input Output
Type States
Pin Description
A(L)
A(E)
Timer Inputs are used either as clock or control signals
depending upon the programmed timer mode These
inputs are active HIGH (or LOW-to-HIGH transitions are
counted) and internally synchronized Timer Inputs must
be tied HIGH when not being used as clock or retrigger
inputs
H(Q)
R(1)
Timer outputs are used to provide single pulse or
continuous waveform generation depending upon the
timer mode selected These outputs are not floated
during a bus hold
A(L)
DMA Request is asserted HIGH by an external device
when it is ready for DMA Channel 0 or 1 to perform a
transfer These signals are level-triggered and internally
synchronized
A(E)
The Non-Maskable Interrupt input causes a Type 2
interrupt An NMI transition from LOW to HIGH is
latched and synchronized internally and initiates the
interrupt at the next instruction boundary NMI must be
asserted for at least one CLKOUT period The Non-
Maskable Interrupt cannot be avoided by programming
A(E)
A(L)
A(E)
A(L)
H(1)
R(Z)
Maskable Interrupt Requests can be requested by
activating one of these pins When configured as inputs
these pins are active HIGH Interrupt Requests are
synchronized internally INT2 and INT3 may be
configured to provide active-LOW interrupt-
acknowledge output signals All interrupt inputs may be
configured to be either edge- or level-triggered To
ensure recognition all interrupt requests must remain
active until the interrupt is acknowledged When Slave
Mode is selected the function of these pins changes
(see Interrupt Controller section of this data sheet)
H(Z)
R(Z)
Address Bus Outputs and Bus Cycle Status (3 – 6)
indicate the four most significant address bits during T₁
These signals are active HIGH
During T₂ T₃ T_W and T₄ the S6 pin is LOW to indicate
a CPU-initiated bus cycle or HIGH to indicate a DMA-
initiated or refresh bus cycle During the same T-states
S3 S4 and S5 are always LOW On the 80C188XL
A15 – A8 provide valid address information for the entire
bus cycle
S(L) H(Z) Address Data Bus signals constitute the time
R(Z)
multiplexed memory or I O address (T₁) and data (T₂
T₃ T_W and T₄) bus The bus is active HIGH For the
80C186XL A₀ is analogous to BHE for the lower byte of
the data bus pins D₇ through D₀ It is LOW during T₁
when a byte is to be transferred onto the lower portion
of the bus in memory or I O operations
NOTE
Pin names in parentheses apply to the 80C188XL
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