80C186XL Datasheet, PDF (26/48 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186XL 80C188XL
AC SPECIFICATIONS (Continued)
MAJOR CYCLE TIMINGS (WRITE CYCLE)
T_A ^e 0 C to ^a70 C V_CC ^e 5V g10%
All timings are measured at 1 5V and 50 pF loading on CLKOUT unless otherwise noted
All output test conditions are with C_L ^e 50 pF
For AC tests input V_IL ^e 0 45V and V_IH ^e 2 4V except at X1 where V_IH ^e V_CC ^b 0 5V
Symbol
Parameter
80C186XL25
Min Max
Values
80C186XL20
Min Max
Test
80C186XL12 Unit _Conditions
Min Max
80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)
T_CHSV
T_CLSH
T_CLAV
T_CLAX
T_CLDV
T_CHDX
T_CHLH
T_LHLL
T_CHLL
T_AVLL
Status Active Delay
Status Inactive Delay
Address Valid Delay
Address Hold
Data Valid Delay
Status Hold Time
ALE Active Delay
ALE Width
ALE Inactive Delay
Address Valid to ALE Low
3
20
3
25
3
35 ns
3
20
3
25
3
35 ns
3
20
3
27
3
36 ns
0
0
0
ns
3
20
3
27
3
36 ns
10
10
10
ns
20
20
25 ns
T_CLCL b 15
T_CLCL b 15
T_CLCL b 15
ns
20
20
25 ns
T_CLCH b 10
T_CLCH b 10
T_CLCH b 15
ns
Equal
Loading
T_LLAX Address Hold from ALE
Inactive
T_CHCL b 10
T_CHCL b 10
T_CHCL b 15
ns Equal
Loading
T_AVCH Address Valid to Clock High
0
0
0
ns
T_CLDOX Data Hold Time
3
3
3
ns
T_CVCTV Control Active Delay 1
3
20
3
25
3
37 ns
T_CVCTX Control Inactive Delay
3
17
3
25
3
37 ns
T_CLCSV Chip-Select Active Delay
3
20
3
25
3
33 ns
T_CXCSX Chip-Select Hold from
T_CLCH b 10
T_CLCH b 10
T_CLCH b 10
ns
Command Inactive
Equal
Loading
T_CHCSX Chip-Select Inactive Delay
T_DXDL DEN Inactive to DT R Low
3
17
3
20
3
30 ns
0
0
0
ns Equal
Loading
T_CLLV LOCK Valid Invalid Delay
3
17
3
22
3
37 ns
80C186XL TIMING RESPONSES (Write Cycle)
T_WLWH WR Pulse Width
T_WHLH WR Inactive to ALE High
2T_CLCL b 15
T_CLCH b 14
2T_CLCL b 20
T_CLCH b 14
2T_CLCL b 25
T_CLCH b 14
ns
ns Equal
Loading
T_WHDX Data Hold after WR
T_CLCL b 10
T_CLCL b 15
T_CLCL b 20
ns Equal
Loading
T_WHDEX WR Inactive to DEN Inactive T_CLCH b 10
T_CLCH b 10
T_CLCH b 10
ns Equal
Loading
26
26