80C186XL Datasheet, PDF (27/48 Pages) Intel Corporation – 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

80C186XL 80C188XL
AC SPECIFICATIONS (Continued)
MAJOR CYCLE TIMINGS (INTERRUPT ACKNOWLEDGE CYCLE)
T_A ^e 0 C to ^a70 C V_CC ^e 5V g10%
All timings are measured at 1 5V and 50 pF loading on CLKOUT unless otherwise noted
All output test conditions are with C_L ^e 50 pF
For AC tests input V_IL ^e 0 45V and V_IH ^e 2 4V except at X1 where V_IH ^e V_CC ^b 0 5V
Symbol
Parameter
80C186XL25
Min Max
Values
80C186XL20
Min Max
Test
80C186XL12 Unit _Conditions
Min Max
80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once)
T_DVCL Data in Setup (A D)
8
10
15
ns
T_CLDX Data in Hold (A D)
3
3
3
ns
80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)
T_CHSV Status Active Delay
3
20
3
25
3
35 ns
T_CLSH Status Inactive Delay
3
20
3
25
3
35 ns
T_CLAV Address Valid Delay
3
20
3
27
3
36 ns
T_AVCH Address Valid to Clock High
0
0
0
ns
T_CLAX Address Hold
0
0
0
ns
T_CLDV Data Valid Delay
3
20
3
27
3
36 ns
T_CHDX Status Hold Time
10
10
10
ns
T_CHLH ALE Active Delay
20
20
25 ns
T_LHLL ALE Width
T_CLCL ^b 15
T_CLCL ^b 15
T_CLCL ^b 15
ns
T_CHLL ALE Inactive Delay
20
20
25 ns
T_AVLL Address Valid to ALE Low T_CLCH ^b 10
T_CLCH ^b 10
T_CLCH ^b 15
ns
Equal
Loading
T_LLAX Address Hold to ALE
Inactive
T_CHCL ^b 10
T_CHCL ^b 10
T_CHCL ^b 15
ns Equal
Loading
T_CLAZ Address Float Delay
T_CLAX 20 T_CLAX 20 T_CLAX 25 ns
T_CVCTV Control Active Delay 1
3
17
3
25
3
37 ns
T_CVCTX Control Inactive Delay
3
17
3
25
3
37 ns
T_DXDL DEN Inactive to DT R Low
0
0
0
ns Equal
Loading
T_CHCTV Control Active Delay 2
T_CVDEX DEN Inactive Delay
(Non-Write Cycles)
3
20
3
22
3
37 ns
3
17
3
22
3
37 ns
T_CLLV LOCK Valid Invalid Delay
3
17
3
22
3
37 ns
27
27