82576EB Datasheet, PDF (28/34 Pages) Intel Corporation – LAN Access Division

Errata - Intel^® 82576EB GbE Controller
27. Tx Packet Lost After PHY Speed Change Using Auto-Negotiation
Problem:
If the PHY establishes a link at 10/100 Mb/s and then auto-negotiation is re-started and a
link is established at 1 Gb/s without resetting the PHY in between, the first 1-to-3 Tx
packets provided by the MAC might not be transmitted.
Implication: This situation is generally seen during testing where the speed of the link partner is
intentionally changed.
During normal operation, the packet loss could occur if the cable was moved to a different
port. In most cases, the higher layers would handle the packet loss and it would not be
visible to the end user.
Workaround: If it is critical that no packets be lost, the software driver could be modified to perform a
PHY reset each time it is notified of a speed change.
Status:
A1, A2 NoFix
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28. PCIe: Wrong Byte Enable Bit Used for Completion Timeout Disable Bit in Device Control 2 Register
Problem:
BE[1] is used to enable the write to the Completion Timeout Disable bit in Device Control
2 register in the configuration space. It should be BE[0] since it is bit 4 in the register.
Implication: If a byte write is used, this bit is not updated since BE[1] is 0b.
The bit could be incorrectly written if a byte write to the high byte is performed. However,
this is unlikely since bits 15:8 are all reserved.
Workaround: Use only word or Dword accesses to the Device Control 2 register.
Status:
A1, A2 NoFix
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29. PCIe: Completion with UR/CA Status Causes Unexpected Completion and Completion Timeout
Errors to be Reported
Problem:
When the 82576 receives a PCIe completion with Unsupported Request (UR) or
Completer Abort (CA) status in response to a request it generated, it reports an
Unexpected Completion error. Because the completion timer is not disabled, a completion
timeout error is reported when the timer expires.
Implication: This situation should not occur in systems that are operating correctly, since all requests
generated by the 82576 are supported.
If an UR/CA status completion is received, the completion timeout error can bring down
the operating system when reported.
Workaround: Not required for systems that are operating correctly.
Note that reporting completion timeout errors can be masked in the Uncorrectable Error
Mask register.
Status:
A1, A2 NoFix
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Intel^® 82576EB GbE Controller
Specification Update
28
Revision: 2.85
September 2012