82576EB Datasheet, PDF (13/34 Pages) Intel Corporation – LAN Access Division

Intel^® 82576EB GbE Controller - Sightings
Table 4. Summary of Sightings, Clarifications, Changes, Errata, Software Clarifications;
Errata Include Steppings (Continued)
44. PF's MSI TLP Might Contain the Wrong Requester ID When a VF Uses MSI-X
A1, A2 NoFix
Software Clarifications
Status
1. While In TCP Segmentation Offload, Each Buffer is Limited to 64 KB
NA
2. Serial Interfaces Programmed By Bit Banging
NA
3. PF/VF Drivers Should Configure Registers That Are Not Reset By VFLR
NA
1.5.1
None.
1.5.2
Sightings
Specification Clarifications
1. PCIe: End Point Request of I/O Space After Initialization
Clarification: The 82576 requests I/O space if EEPROM bit 14, word 0x19 is set. When this EEPROM bit
is set, I/O Space is always requested.
The specification does not define a way to signal that IO BAR usage is done. When PCIe
compliance tests are run, this may cause a test failure.
Failure when running PCI SIG compliance tests with EEPROM bit 14, word 0x19 set.
Workaround: Disable I/O BAR requests via EEPROM bit 14, word 0x19. Since various pre-boot SW tools
require the I/O Space be requested, the bit is enabled by default in EEPROM images.
▼ Return to Summary
2. PCIe: Partial Memory-Write Requests Actually Writing Full DW
Clarification: The PCIe specification allows a device not to accept certain requests. This is under
"programming model" cases. The device needs to issue a Completer Abort error if specific
request violates the programming model. As part of its programming model, the 82576
does not support writes and reads with Byte Enables to specific memory addresses. Such
writes will be fully executed and will not be treated as completion abort.
CSR writes and reads with partial (or zero) Byte Enables will be executed (in specific
address ranges). This scenario will not happen when using the device driver and this
functionality is also not needed for the normal operation of the design.
Workaround: No partial (zero) Byte Enables writing and reading to the device.
▼ Return to Summary
3. PCIe: Completion Timeout Mechanism Compliance
Clarification: PCIe Completion Timeout value must be properly set.
The 82576 Completion Timeout Value(3:0) must be properly set by the system BIOS in
Intel PCIe Configuration Space Device Control 2 Register (0xC8; RW). Failure to do so
can cause unpredictable system behavior.
Revision: 2.85
September 2012
Intel^® 82576EB GbE Controller
Specification Update
13