82544EI Datasheet, PDF (28/52 Pages) Intel Corporation – Gigabit Ethernet Controller

82544EI Gigabit Ethernet Controller Networking Silicon Datasheet
4.5.1.2
PCI/PCI-X BUS Interface Timing
Table 13. PCI/PCI-X BUS Interface Timing Parameters^{a, b, c}
Symbol
Parameter
PCI-X 133 MHz PCI-X 66 MHz
Min Max Min Max
PCI 66 MHz
Min Max
PCI 33 MHz
Min Max
Units
Note
s
T_VAL
CLK to Signal Valid Delay
- bused signals
0.7
3.8
0.7
3.8
2
6
2
11
T_VAL(ptp)
CLK to Signal Valid Delay
- point-to-point signals
0.7
3.8
0.7
3.8
2
6
2
12
T_ON
T_OFF
T_SU
Float to Active Delay
Active to Float Delay
Input Setup Time to -
bused signals
0
0
7
7
1.2
1.7
2
2
14
28
3
7
T_SU(ptp)
Input Setup Time to CLK -
point-to-point signals
1.2
1.7
5
10,12
T_H
T_RRSU
T_RRH
Input Hold Time from CLK
REQ64# to RST# setup
time
RST# to REQ64# hold
time
0.5
10*
T_CYC
0
0.5
10*
T_CYC
0
0
10*
T_CYC
0
0
10*
T_CYC
0
ns a,b,c
ns a,b,c
ns
a
ns
a
ns
c
ns
c
ns
ns
ns
a. Output timing measurement as shown.
b. REQ# and GNT# are point-to-point signals, and have different output valid delay and input set up times than do bused signals. GNT# has a set
up of 10; REQ# has a set up of 12. All other signals are bused
c. Input timing measurement as shown.
Figure 4. PCI Bus Interface Output Timing Measurement Conditions
VTH
PCI_CLK
VTEST
VTL
Output
Delay
Tri-State
Output
VTEST
VSTEP(3.3VSignalling)
output current≤ leakage current
TON
TOFF
24
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